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inner bus
相关语句
  客车内
     Fuzzy Design of Inner Bus Decoration
     基于模糊技术的客车内饰设计
短句来源
     :Because of more requirements from bus style and performance, as well as economy and ergonomics, there are less standards on design scheme to inner bus decoration.
     由于风格、性能要求、经济性要求和人机工程等需求,客车内饰布置设计难以规范。
短句来源
     With the fuzzy technology, an inner bus decoration design system has been developed.
     本文描述了模糊技术在客车内饰布置设计中的开发应用。
短句来源
  “inner bus”译为未确定词的双语例句
     1. Both PCI Master and PCI Slave bus protocols on the inner of the PCI interface are established. They are the first inner bus protocol of PCI in China, which is in compliance with the standard of VSIA.
     1.制定了PCI总线接口内侧主PCI(PCI Master)总线协议和从PCI(PCISlave)总线协议,提出了我国第一个符合VSIA标准的PCI内侧总线协议。
短句来源
     The TMS320DM642 chip of Ti is used on the hardware platform, which has perfect video/audio input/output ports and provides the perfect juncture. Memorizer is composing of 4M*8 flash and 4M*8 SDRAM. The video code chip is Philips ' SAA7121 and decode chip is Tl's TVP5150. Inner bus is IIC and pioneer-time-619 CCD videos and 9's LCD screen device are selected.
     硬件实验平台的核心DSP芯片采用TI的TMS320DM642,有完善的视频/音频的输入输出接口,存储器为4M~*8位的Flash和4M~*8位的SDRAM,选用了Philips的SAA7121视频采集芯片和TI的TVP5150视频输出接口芯片,配置了先锋时代619的CCD摄像机和9寸液晶显示屏。
短句来源
     Then it brings forward the two application manners that are standard Host application and the usage as inner bus.
     然后提出了PCMCIA 接口在嵌入式系统中的两种应用方式,即标准Host 端应用和内部总线应用。
短句来源
     Dual PCMCIA Ethernet expansion as the inner bus application, it analyzes the working mechanism of the interface, the key problem of the realization and simplifies the system architecture within a certain degree.
     采用双以太网接口扩展作为内部总线应用和IO 扩展的代表,深入的分析了接口的工作机制,重点阐述了关键技术的使用和实现中需要解决的问题,对系统结构进行了适当的精简。
短句来源
     The innovative design ways for two stage measurement and controlling network are introduced, such as SPI bus qua inner bus for single chip microprocessor system, the characteristic of single chip microprocessor parallel simulating, the technique of CAN testing oneself, and offers design frame for hardware and software.
     对两级测控网络实验开发系统中的几个创新的设计思路进行了简介,如以SPI作为内部总线的单片机小系统、单片机的并行仿真模式的特点和CAN网络的自测试方法等,并提供了硬件和软件的设计框图。
短句来源
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  相似匹配句对
     On The Bus
     公交车上
短句来源
     The Inner Communication Bus of AUV
     AUV内部通讯总线设计
短句来源
     Fuzzy Design of Inner Bus Decoration
     基于模糊技术的客车内饰设计
短句来源
     M-BUS and Its Application
     M-BUS总线及其应用
短句来源
     Inner Wild
     内敛的狂野
短句来源
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  inner bus
The value z was 0.001 ms, which was obtained by 1526bytes/9Gbps, because the inner bus speed was 9 Gbps in the L3SW.
      


:Because of more requirements from bus style and performance, as well as economy and ergonomics, there are less standards on design scheme to inner bus decoration. With the fuzzy technology, an inner bus decoration design system has been developed. The system contains 3 dimension inner parts modeling and some analysis in the virtual environment, for example, accessibility and convenience evaluation with Chinese manikin. After the fuzzy evaluation to the inner decoration design scheme,...

:Because of more requirements from bus style and performance, as well as economy and ergonomics, there are less standards on design scheme to inner bus decoration. With the fuzzy technology, an inner bus decoration design system has been developed. The system contains 3 dimension inner parts modeling and some analysis in the virtual environment, for example, accessibility and convenience evaluation with Chinese manikin. After the fuzzy evaluation to the inner decoration design scheme, the redesign decision can be made.

由于风格、性能要求、经济性要求和人机工程等需求,客车内饰布置设计难以规范。本文描述了模糊技术在客车内饰布置设计中的开发应用。该应用系统首先进行内饰件三维造型设计,调入内饰件到虚拟现实环境中,利用中国人体模型进行可及性、视野等人机工程的测量分析,对测量结果进行模糊评价,然后通过模糊规则进行内饰件的再设计决策。

The innovative design ways for two stage measurement and controlling network are introduced, such as SPI bus qua inner bus for single chip microprocessor system, the characteristic of single chip microprocessor parallel simulating, the technique of CAN testing oneself, and offers design frame for hardware and software.

对两级测控网络实验开发系统中的几个创新的设计思路进行了简介,如以SPI作为内部总线的单片机小系统、单片机的并行仿真模式的特点和CAN网络的自测试方法等,并提供了硬件和软件的设计框图。

This article gives a method of implementation of HDLC with a double-core chip Triscend E5.The HDLC Frame structure and its corresponding control modules are realized by the Configurable System Logic(CSL) on chip while the interactions between CSL and MCU are realized with DMA channels intograted in the chip and inner bus.Compared to conventional methods such as soft programming or pure FGPA,the method presented has the advantage of high flexibility,low complexity,great efficiency,high scale of integration...

This article gives a method of implementation of HDLC with a double-core chip Triscend E5.The HDLC Frame structure and its corresponding control modules are realized by the Configurable System Logic(CSL) on chip while the interactions between CSL and MCU are realized with DMA channels intograted in the chip and inner bus.Compared to conventional methods such as soft programming or pure FGPA,the method presented has the advantage of high flexibility,low complexity,great efficiency,high scale of integration and low power consumption.

给出了一种以8032微处理器为核、配备了FPGA(现场可编程门阵列)的双核芯片E5CSoC(可配置系统芯片)实现HDLC(高级数据链路控制)逻辑的方法,该方法利用片上的CSL(可配置系统逻辑)实现HDLC的帧结构和相关控制模块,并利用片内总线和片内集成的DMA(直接存储器存取)通道实现CSL和MCU(单片机)的数据交换,从而完成整个HDLC功能。该方法相对于专用芯片或FPGA实现表现出突出的灵活性、高效性,且集成度高、功耗小。

 
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