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 combinational logic 组合逻辑(42)组合逻辑电路(50)复合逻辑(1)
 组合逻辑
 Combinational Logic Control of SIL-200 Y-Molecular Sieve Vertical Roasting Stove SIL-200 Y型分子筛立式焙烧炉的组合逻辑控制 短句来源 SDT Algorithm for Diagnosis of Combinational Logic Networks 诊断组合逻辑网络的SDT算法 短句来源 Combinational Logic and Clocking Schemes in FPGA Design FPGA设计中的组合逻辑与时钟方案 短句来源 A Combinational Logic B/BCD Conversion for any BCD Code 任意BCD码的B/BCD组合逻辑变换网络 短句来源 Multi-Fault Diagnosis for Combinational Logic Circuits 组合逻辑多故障诊断 短句来源 更多
 组合逻辑电路
 Using Java to Realize the Combinational Logic Circuit Simulation Platform 用Java实现组合逻辑电路仿真平台 短句来源 N (23,12) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-OR gates. N(23,12)是一个异步的组合逻辑电路,能用12个大数逻辑门和77个异或门电路来实现。 短句来源 Fabricated in a CMOS/LDMOS process based on SDB/SOI substrate,the circuit contains a D/A converter,a dual-channel comparator,flip-flops,and combinational logic circuits,as well as over-frequency and over-voltage protection circuits. 该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。 短句来源 The Application of Data Selector in the Combinational Logic Circuit 数据选择器在组合逻辑电路中的应用 短句来源 Discuss the way of communal technique to design combinational logic circuits 公用技术组合逻辑电路设计方法的初步探讨 短句来源 更多
 复合逻辑
 Experimental results for 16 combinational logic operation in an 8f coherent optical processing system are shown. 也给出了在8f相干光学处理系统中执行的16种复合逻辑运算的结果。 短句来源
 “combinational logic”译为未确定词的双语例句
 Neural networks based test generation algorithm for combinational logic circuits 基于神经网络的组合电路测试生成算法 短句来源 Research on Test Technology of Combinational Logic Circuits in the Control System of Magnetic Bearings 磁力轴承控制系统中组合电路测试技术研究 短句来源 Study on Chaos Control and Chaotic Optimization with Its Applications in Test Generation for Combinational Logic Circuits 混沌控制与混沌优化及其在组合电路测试生成中的应用研究 短句来源 A DECOMPOSITION METHOD FOR SIMPLIFYING COMBINATIONAL LOGIC DESIGN BASED ON BOOLEAN EQUATION 一个基于布尔方程的简化组合逻辑设计的分解方法 短句来源 The Design of MSI Combinational Logic Circuit MSI组合逻辑设计 短句来源 更多

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 combinational logic
 Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least $10 \times$saving in hardware resource. One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. By reducing the number of binary inputs to combinational logic and merging algorithm steps, the strategy creates new simplified functions to decrease logic depth and area. The synchronization of internal computations is achieved by balancing inherent RC delays of combinational logic elements, thus allowing circuits to be pipelined at a very fine-grain level. Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG 更多
 This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic. There are nine examples of experiments in this manual.Every experiment is designed by using Karnaugh map to realize logic circuits, and test circuits to conduct the tests. 本实验指导书分为两大部分:组合逻辑,时序逻辑。共有九个实验。 每个实验都是从设计着手,通过卡诺图,实现逻辑电路,然后组成测试电路进行试验。 In accordance with Doolean Difference we have in many documents put out the algorithm of the complete test sets. Its prominnet features are the clarity and precision of deduction, However its shortomings are: (1). The accurate value we obtained when there is no fault between test code and the combinational logic network cannot be decided immediately; (2). High Complexitg of computation exists and especially in the structure of the reconverging fan-out.I herein propose the conception of Boolean orientable... In accordance with Doolean Difference we have in many documents put out the algorithm of the complete test sets. Its prominnet features are the clarity and precision of deduction, However its shortomings are: (1). The accurate value we obtained when there is no fault between test code and the combinational logic network cannot be decided immediately; (2). High Complexitg of computation exists and especially in the structure of the reconverging fan-out.I herein propose the conception of Boolean orientable difference and the path along with Boolean Difference, in the meantime, taking this proposition as a basis I am trying to establish the algorithm of combinational logic network fault diagnosis test sets.I believe the couple of the shortcomings mentioned above can be overcome. 许多文章利用布尔差分的概念建立故障完全测试集的算法。其优点是推导清晰严谨,但其缺点是,一、所求得的测试码对应组合逻辑网络无故障时的正确输出值不能立即确定。二、计算复杂性高,特别对扇出再收敛型结构更为如此。本文作者提出布尔方向差分和沿通路布尔差分的概念,并以此为基础建立一种组合逻辑网络故障诊断测试集的算法。上述两个缺点可以克服。 Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher. First, we find out a new and systematical approaoh to identify all hazards of a given logic circuit on the basis of "Four-Valued Logic and Star Algorithm" , then derive formalae of hazardous tests for single or multiple stuck-at faulls and... Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher. First, we find out a new and systematical approaoh to identify all hazards of a given logic circuit on the basis of "Four-Valued Logic and Star Algorithm" , then derive formalae of hazardous tests for single or multiple stuck-at faulls and for bridging faults which are undetectable statically, and a number of examples are taken, 本文系统地研究了组合逻辑线路的动态测试,给出了生成一个动态可测故障以及一个冒险可测故障(静态不可测)完全测试集的方法。首先在“四值逻辑和星算法”的基础上,导出了一个识别逻辑线路所有(静态和动态)冒险的一个新的、系统的方法,然后应用获得的结果,推导了静态不可测单固定故障、多固定故障以及桥接故障的冒险测试公式,并举出了若干实例。 << 更多相关文摘
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