On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up.
This paper introduces the characterlistics of VHSIC hardware description language. The difference between VHDL and computer advanced language, as well as the limitations of register RTL are discussed, and the methods of reducing the occupying rate of the hardware resource in design of programmable application specific integrated circuit are presented.
This paper discusses sequential logic synthesis systematically. On the basis of analyzing the format of RTL descriptions written by users, it presents a synthesis method which can synthesize both basic sequential logic circuits and complex sequential logic circuits which some other systems do not introduce, at the end of this paper, it shows some concrete examples.