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   rtl 8019 在 计算机硬件技术 分类中 的翻译结果: 查询用时:0.667秒
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  rtl级
    In order to meet the requirement of Time to market and function enrichment, more and more advanced design company shift to a new abstract design level for complex DSP application, i.e. from RTL to C/C++ level, to keep their leading position.
    为了满足产品上市时间和功能丰富性的要求,越来越多的先进设计公司开始提高设计的抽象层次进行复杂的DSP硬件设计,从RTL级提高到C/C++,以保持产品的持续领先地位。
短句来源
    On the platform of Intel Xeon 2.4GHz, the speed of this methodology is about 300K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.
    在2.4GHz的IntelXeon上,该功耗评估方法的速度约为300K/s,是RTL级的评估方法的5000倍,而且误差很小.
短句来源
    Establishment and Simulation of Neural Processor Slices Algorithmic Level and RTL Level Models with VHDL
    神经元计算芯片的VHDL算法级与RTL级模型的建立及模拟
短句来源
    Synthesizable Circuit Model in RTL
    可综合RTL级电路模型
短句来源
    Design and Realization of USB 2.0’s Protocol Layer Based on RTL
    基于RTL级USB2.0协议层的设计与实现
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  芯片rtl
    Test Method of DSP Chip RTL Based on XML
    基于XML的DSP芯片RTL级测试方法
短句来源
    The detail is the dealed data is transferred to DSP through PC, after dealing ,combining μC/OS-Ⅱ and NIC RTL8019AS We accomplished data transmission in Internet.
    本系统设计的是PC机通过串行接口把待处理的数据送给DSP,经处理后结合μC/OS-Ⅱ嵌入式操作系统和网卡控制芯片RTL8019AS实现网络传输。
短句来源
    1. Theory of hardware system is given, and concrete configuration and character of 89C52 and inside configuration and registers of RTL8019AS are discussed importantly.
    1.给出了硬件系统的设计原理框图,着重讨论了硬件系统的嵌入式微控制器89C52各个组成部分的具体结构特点和网卡控制芯片RTL8019AS的内部结构以及寄存器。
短句来源
    The feature of hardware which is mainly composed of C8051F020 and RTL8019AS is explained in detail, and software protocol and good application prospect of the system are summarized.
    详尽阐述了以单片机C8051F020和以太网控制芯片RTL8019AS为主要结构的硬件特点,进一步概述了实现的软件协议以及该系统所具有的良好的应用前景.
短句来源
    The Ethernet microcontroller RTL8019AS is presented ,TCP/IP protocol is embedded in MCU to implement data transmission between intelligent equipments and meters with local network/Ethernet by RTL8019AS .
    介绍了以太网控制器芯片RTL8019AS,并将TCP/IP协议嵌入通用单片机中,通过RTL8019AS实现了智能设备和仪表在局域网/因特网上的数据传输。
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  rtl描述
    The soft-core is designed by using top-down methodology. The thesis discusses the whole design and verification of Turibo-51's CPU, including system partition, redesign of the instruction's timing, design of data paths and controlling logics, synthesizable RTL code, simulation, synthesis and FPGA verification.
    本文采用自上而下的正向设计流程,重新安排了8051指令的执行时序,完成了CPU的系统结构划分,数据通道和控制逻辑设计,以及可综合RTL描述,仿真综合,FPGA验证等一系列的工作,完整地实现了软核的设计和验证。
短句来源
    By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.
    提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 . 此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径
短句来源
    This article discusses the synthesis of latches and flip flops described in RTL form with VHDL language, clarifies the different cases of using latches and flip flops in detail, and shows how to distinguish latches from flip flops correctly.
    文中从 VHDL 语言的 RTL 描述特征入手 ,研究了 RTL 综合中锁存器与触发器的综合方法 ,阐述了采用锁存器及触发器的各种不同情况 ,同时说明如何才能正确地区分锁存器及触发器 .
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GCC is a successful system which supports a few high level languagesas well as many machines. Before adding something to its front end or making it runn onsome other system,analysis of its intermediate language RTL becomes a prerequisite.The back end information MDs in GCC are written in textual form of RTL,MDs areused to define instruction sets ,function units,delay slots,etc. GCC uses a set of pro-grams gen * to produce a set of C files inse-*, which give the machine information tothe complier...

GCC is a successful system which supports a few high level languagesas well as many machines. Before adding something to its front end or making it runn onsome other system,analysis of its intermediate language RTL becomes a prerequisite.The back end information MDs in GCC are written in textual form of RTL,MDs areused to define instruction sets ,function units,delay slots,etc. GCC uses a set of pro-grams gen * to produce a set of C files inse-*, which give the machine information tothe complier in GCC directly. Gen* can be considered as the complier of MD.

GCC是一个成功地支持多种高级语言和多种机器平台的系统,分析其中间语言RTL是扩充其前端和移植GCC的前提。GCC的后端信息MD使用RTL的外部形式书写,主要用于定义机器的指令集、功能部件、延迟特性等。GCC提供一套MD的转换程序gen*来生成一套C文件insn-*,供编译体更有效地获取与机器有关的信息;可以把gen*看作是MD的编译器。

he authors proposed a new methedology for FPGA design. Starting froma high-level,supported by a high-level synthesis system BITHLS,the behavioral design description is converted to the RTL structural design (a netlist). Then, based on the unit library provided by an FPGA vendor (e. g. Xilinx), the RTL netlist is mapped to the appropriate data format acceptable to the FPGA development system for constucting the real design.

本文提出了一种从较高的行为级描述进行FPGA设计,从而替代传统的以原理图作为设计输入的方法。通过高级综合,可以把用户所给出的行为功能描述自动转化为较低层次的结构描述,并进一步与FPGA设计系统相连完成最终设计。

The methods to establish and simulate VHDL models of complex circuits are discussed in accordance with the instruction and system structure of neural processor slice. The slices algorithmic level and RTL level descriptions are given. The Two descriptions are simulated on the same test bench, verifying the correctness of both and equivalence of their functions. From this paper, we can see that the VHDLs powerful capacity of describing hardware will bring out constantly rising the level of circuit designs....

The methods to establish and simulate VHDL models of complex circuits are discussed in accordance with the instruction and system structure of neural processor slice. The slices algorithmic level and RTL level descriptions are given. The Two descriptions are simulated on the same test bench, verifying the correctness of both and equivalence of their functions. From this paper, we can see that the VHDLs powerful capacity of describing hardware will bring out constantly rising the level of circuit designs.

本文针对神经元计算芯片的指令系统和体系结构,详细讨论了复杂电路的VHDL建模及模拟验证方法,分别给出了该芯片的算法级描述和RTL级描述,并用相同的测试台对两级描述进行了模拟,验证了描述的正确性和功能的等价性.不难看出,VHDL语言描述硬件电路的强大能力为电路设计层次的不断提高创造了必要的条件

 
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