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synthesis flow
相关语句
  综合流程
     The Logic Synthesis Flow for ePro System
     ePro系统的逻辑综合流程
短句来源
     Its token transfer level model was in SystemC language. A synchronous EDA tools based and standard cell based asynchronous circuit synthesis flow was developed.
     采用了SystemC语言进行令牌传输级建模,开发了基于同步EDA工具和标准单元的异步电路综合流程
短句来源
     A synthesis flow of low power consumption CMOS circuit has been introduced.
     针对CMOS电路的功耗来源提出了一种低功耗综合流程.
短句来源
     For Example, Catapult synthesis can rapidly explore multiple architectures to quickly find the best implementation for performance, area and power in FIR implementation, and make the true IP reuse possible. It also provides the area、delay and throughput(36、3、1 clock cycles) under the different constraints by table and graphics, and integrates the verification and RTL synthesis flow, so that it will improve the design efficient greatly。
     本文以FIR的实现为例,利用Catapult Synthesis快速探索不同的设计架构,快速地找到性能、面积和功耗之间折衷的最佳实现方案,使得真正的IP复用成为可能,并以图表方式给出不同约束下的面积、延迟和吞吐率(36、3、1时钟周期)的性能,同时提供了集成的验证和综合流程,极大地提高了设计效率。
短句来源
  “synthesis flow”译为未确定词的双语例句
     A logic synthesis flow of low power consumption CMOS circuit
     CMOS电路的低功耗逻辑综合
短句来源
     The effect of constitute of soft segments and hard segments, structure, relative molecular weight, chain extender, isocyanate index(R) and synthesis flow condition on the mechanical properties, crystallinity, binding properties, heat-resistance properties are studied.
     研究了软硬段组成、结构、相对分子质量、扩链剂、异氰酸酯指数(R)及合成工艺条件等对聚氨酯热熔胶的力学性能、结晶性能、粘接性能、耐热性能的影响。
短句来源
     The effect of isocyanate index, kinds and amount of chain extender and relative molecular mass of polyurethane on the properties of polyurethane hot melt adhesives is studied, make sure the synthesis flow condition of polyurethane hot melt adhesives (reaction temperature, prepolymerization time, chain extender time and so on).
     考察了异氰酸酯指数、扩链剂种类、用量及聚氨酯相对分子质量对聚氨酯热熔胶性能的影响,确定了聚氨酯热熔胶的合成工艺条件(反应温度、预聚时间、扩链时间等)。
短句来源
  相似匹配句对
     Synthesis of p
     对氯苯甲醛的合成
短句来源
     The Synthesis and Study on Diesel Flow Improvers
     柴油低温流动性能改进剂的研制
短句来源
     The Logic Synthesis Flow for ePro System
     ePro系统的逻辑综合流程
短句来源
     The Synthesis of Triethylorlorthoacetate
     原乙酸三乙酯的合成
短句来源
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  synthesis flow
We should note that Synopsys are working to improve those results, but in the meantime we recommend on the SystemC RTL synthesis flow.
      
We present two such models for quadratic placement and discuss how they can be incorporated in a practical physical synthesis flow.
      
We describe the COSMECA co-synthesis flow in more detail in this section.
      
The synthesis flow which employs watermarking of combinational logic synthesis solutions encompasses several phases illustrated in Figure 3.
      
The synthesis flow which employs watermarking of combinational logic synthesis solutions encompasses several phases illustrated in Figure 1.
      
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This report describes a layout synthesis system called AISCE. The system accepts structural or logic hardware design specification and creates physical layout of integrated circuit automatically. AISCE contains several parts: schematic capture system, netlist compiler, module generators for data and control path, tools for floorplanning, placement and routing, simulators and verifiers, etc.. They are all integrated into one design framework. Following AISCE's synthesis flow, this paper introduces each...

This report describes a layout synthesis system called AISCE. The system accepts structural or logic hardware design specification and creates physical layout of integrated circuit automatically. AISCE contains several parts: schematic capture system, netlist compiler, module generators for data and control path, tools for floorplanning, placement and routing, simulators and verifiers, etc.. They are all integrated into one design framework. Following AISCE's synthesis flow, this paper introduces each part of the system. Experimental results show that AISCE is an efficient and promising system.

本文从设计思想和实现路线两方面介绍了一个超大规模集成电路的自动化设计系统-AISCE系统。这是一个结构级版图自动综合系统,针对不同的设计,可以采用结构级硬件描述语言对电路进行描述,并通过优化和综合自动产生最终版图;也可以通过逻辑图编辑器对电路进行交互式编辑或通过输入电路网表对电路进行版图综合产生最终版图。对系统实际使用的验证表明,该系统具有较高的执行效率和广泛的应用前景。

This paper presents a vector field visualization approach based on texture synthesis. The approach primarily adopts patch-based texture synthesis flow, synthesizing progressively-variant textures to reflect the diversification trend of vector fields. In the approach, the basic synthesis patches are divided adaptively into multi-layer, multiform sub-patches to fit the variety of vector field. In some patches where the inside vector data vary acutely, the pixel-based texture synthesis is adopted...

This paper presents a vector field visualization approach based on texture synthesis. The approach primarily adopts patch-based texture synthesis flow, synthesizing progressively-variant textures to reflect the diversification trend of vector fields. In the approach, the basic synthesis patches are divided adaptively into multi-layer, multiform sub-patches to fit the variety of vector field. In some patches where the inside vector data vary acutely, the pixel-based texture synthesis is adopted to preserve the smoothness of the synthesis results. Experimental results show that our method can generate appropriate textures to clearly exhibit the diversifications trend of module and direction in vector fields, achieving fast and high-qualified vector field visualization.

在纹理合成过程中利用向量场作为指导,生成反映向量场大小和方向变化的合成结果·采用块纹理合成的流程,在对向量场合成块均匀划分的基础上,通过进一步的自适应分割,将向量场划分成为不同大小和不同形状的最终合成块,使之与向量场的变化趋势相吻合·对向量变化过于剧烈的区域,则采用点合成的方式进行纹理合成,以保证合成效果的平滑·实验表明,文中的方法可以实现快速而高质量的向量场可视化·

A synthesis flow of low power consumption CMOS circuit has been introduced.This flow could use the gated clock,the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.This technology has been used to design a PTC(PWM/Timer/Counter) controller,and the results indicated that 57% of the circuit power consumption has been reduced,while only 21% compared reduced if only the technology of gated clock was used.

针对CMOS电路的功耗来源提出了一种低功耗综合流程.这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗.对一个PTC(PWM/Timer/Counter)控制器的仿真表明,这种流程可以降低电路功耗57%,与仅使用门控时钟的流程相比可以进一步降低电路功耗21%.

 
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