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bit
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    A HIGH SPEED ECL 256×1 BIT RAM
    高速ECL256字×1随机存储器
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    An ECL 1024×1 Bit RAM
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    A 32 Bit Programmable Signal Processor for a Multiprocessor System Environment.
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  比特
    Programmable and Integrable Hybrid Optoelectronic Liquid Crystal Encoded 32 bit Full-adder Module
    可编程可集成光电混合液晶编码32比特加法器模块
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    InGaAs/InGaAsP/InP SAGM-APD for Long-Haul High Bit Rate Optical Fiber Communications
    长距离高比特率光纤通信用InGaAs/InGaAsP/InP SAGM-APD
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    Study of 1 Bit High Order ΣΔ Modulators
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    The Scheme for a Bit Leaking Circuit Used in VC 4/E1 Demapping ASICs
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    比特并行Reed-Solomon编码器的设计
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  “bit”译为未确定词的双语例句
    THE BIT ERROR RATE MEASUREMENT OF THE METEOROLOGICAL SATELLITE HRPT SYSTEM
    气象卫星HRPT系统的误码率测量
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    A study of the 0~255 bit program controlled code waveform
    0~255 bit可程控编码波形的研究
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    Ti: LiNbO_3 M-Z Intensity Modulator for Long Haul,High Bit Rate Optical Fiber Communication Systems
    适于长距离、高速率光纤通信系统的Ti:LiNbO_3M-Z型强度调制器
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    Study on LD-CELP Coder at the Bit Rate of 8 Kb/s
    8Kb/sLD-CELP编码器的研究
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    The Bit Error Rate of Soliton Communication System with Control of Phase Modulation and Dispersion Compensation
    位相共轭及色散补偿孤子通信系统的误码率
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  bit
Experimental results show that the proposed approach can reduce the computational cost of full search and fast multi-block motion estimation by 80 % and 45 %, respectively, with similar visual quality and bit rate.
      
The proposed algorithm also reduces by 75 % the computational cost of the large-small mode isolation algorithm for low-motion sequence coding, and with 0.06 PSNR gain and 3.7 % reduction in bit rate.
      
In underwater acoustic communication, because the available bandwidth of the channel is severely limited, the direct-sequence spread-spectrum scheme can only be realized at low bit rates.
      
The bit error performance is correlative not only with the interference-signal ratio (ISR), the frequency offset and the phase of the CW interference sensitively, but also with the individual spread spectrum code sequence.
      
DCT_M model for excitation parameter in low bit rate vocoder
      
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An experimental 1024-bit MOS RAM was fabricated by the P-channel silicon gate process. The design is of the standard 4-transistor cell type, but with some modifications in the peripherial circuits: 1. a grounded device, which is controlled by the internal clock, being used in series with the address decoder, to cut off the dc path, reducing the power ; 2. a clocked single transistor being used as a gate to simplify the address latch; and 3. a grounded device of low transconductance added to the word line,...

An experimental 1024-bit MOS RAM was fabricated by the P-channel silicon gate process. The design is of the standard 4-transistor cell type, but with some modifications in the peripherial circuits: 1. a grounded device, which is controlled by the internal clock, being used in series with the address decoder, to cut off the dc path, reducing the power ; 2. a clocked single transistor being used as a gate to simplify the address latch; and 3. a grounded device of low transconductance added to the word line, raising the noise margin.

本文介绍一种1024位MOS随机存储器电路。采用P沟硅栅工艺,标准的四管单元结构。电路设计的主要特点是:1.在地址译码器中串入由内部时钟控制的接地管,完全消除了直流通路,使功耗大大降低;2.地址码封锁电路采用了一种由时钟控制的单管门形式,简化了电路;3.字线通过一个小跨导的放电管接地,提高了抗干扰能力。

A new high speed integrated logic has been described. Instead of a single type of cell gate which is used in most logic IC's, the new logic here described is based on several types of basic cells to synthesize a logic system. Therefore, the threshold characteristic will not be the common requirement for each type of cell gates. The main logic unit in DYL is a very high-speed linear AND-OR gate made with simple technology (without threshold). A four-bit full adder carry chain specimen has been developed...

A new high speed integrated logic has been described. Instead of a single type of cell gate which is used in most logic IC's, the new logic here described is based on several types of basic cells to synthesize a logic system. Therefore, the threshold characteristic will not be the common requirement for each type of cell gates. The main logic unit in DYL is a very high-speed linear AND-OR gate made with simple technology (without threshold). A four-bit full adder carry chain specimen has been developed with wide-line photolithography. It's time-delay measured for each carry stage is about 1 ns for the front edge of the signal and even much smaller for the trailing edge. The maximum power dissipation per gate is about 12.5mW. This new logic has been analysed and compared with several conventional integrated logic circuits.

介绍了一种新的高速集成逻辑电路。它不同于常用集成逻辑电路那样基于一种基本单元门电路,而是由几种基本单元组合而成所需的逻辑系统,因而并不要求每种基本单元都有阈值特性。其主要基本单元就是一种高速线性“与或”门,工艺很简单。用较粗尺寸工艺试作的四位全加器进位链样品,实测速度为每级进位上升边延迟1ns,下降边延迟更小。每门最大功耗12.5mw。文中还与几种原有的集成辑逻电路进行了分析比较。

In this paper some improvements of DCCL full adder have been presented. They simplify the structure and reduce the clock pulses numbers to three. Two of them are the same as those of the ordinary two phase CCD.This is of great significance for combining CCD memory with DCCL to develop a monolithic signal processing system. A 2-word 2-bit adder has been fabricated using conventional MOS technology. Design considerations and experimental results are also given.

本文提出了简化数字式电荷耦合逻辑(DCCL)全加器结构的实现方法。此法可使这种全加器的时钟脉冲减少到三种,而且其中的两种与普通二相电荷耦合器件(CCD)的时钟系统完全一致,这对发展CCD存储与DCCL相结合的单片式信息处理系统有重大意义。文中给出了用常规的MOS工艺制造二位加法器的设计原理与实验结果。

 
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