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prefetch mechanism
相关语句
  预取机制
     The Design and Implementation of a Effective Prefetch Mechanism
     一种高效预取机制的设计与实现
短句来源
     To implement uninterrupted parallel instruction stream delivery, a prefetch mechanism of fetch unit level was researched and designed, which greatly improved the pipeline efficiency.
     为了实现“源源不断”,本课题研究并设计实现了取指部件级的指令预取机制,大大提高了指令流水线的运行效率,对于标准测试程序的总执行时间比YHFT-D4缩短了5.15%。
短句来源
  “prefetch mechanism”译为未确定词的双语例句
     3. Given a model of superscalar dual issue microprocessor, described the pipeline, instruction prefetch mechanism and execution strategy of the model.
     3.建立了一个X86指令双发射的微处理器模型,介绍了该处理器模型流水线的划分,描述了指令前段取指策略及指令如何并行执行,给出了双发射指令译码的设计思路。
短句来源
     the function of these portions and the prefetch mechanism which can advance the efficiency by increasing the hit rate and reducing the memory access time.
     各部分完成的功能以及为提高命中率和降低存取时间,从而提高效率而采取的预取处理机制;
短句来源
  相似匹配句对
     The Design and Implementation of a Effective Prefetch Mechanism
     一种高效预取机制的设计与实现
短句来源
     The mechanism was discussed.
     对其超增感作用机理作了初步的分析探讨。
短句来源
     The Mechanism of Thinking
     思维机制探索
短句来源
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The efficiency of microprocessor memory is very important to its holistic capability.It introduces the architecture of Intel P4 Microprocessor memory, includes L1 data Cache, L2 Cache, Trace Cache; the function of these portions and the prefetch mechanism which can advance the efficiency by increasing the hit rate and reducing the memory access time. To reduce the access time which can increase the holistic capability of microprocessor, P4 microprocessor adopts these ways: hiberarchy-design, bulky L2 Cache...

The efficiency of microprocessor memory is very important to its holistic capability.It introduces the architecture of Intel P4 Microprocessor memory, includes L1 data Cache, L2 Cache, Trace Cache; the function of these portions and the prefetch mechanism which can advance the efficiency by increasing the hit rate and reducing the memory access time. To reduce the access time which can increase the holistic capability of microprocessor, P4 microprocessor adopts these ways: hiberarchy-design, bulky L2 Cache and applying prefetcher which can increase the hit rate of cache and reduce the cost of hit failed.

处理器存储系统的效率对其整体性能有着十分重要的作用。文中介绍了P4处理器内存的体系结构,它包括一级数据Cache、二级Cache、TraceCache;各部分完成的功能以及为提高命中率和降低存取时间,从而提高效率而采取的预取处理机制;P4处理器主要采取具有层次结构的内存设计、大容量的二级Cache和在跟踪Cache中采用预取处理机制的方法来提高Cache的命中率和降低未命中的代价来缩短处理器的访问时间,最终达到提高处理器整体性能的目的。

The paper presents a two-level cache structure based on CD-ROM-mirroring servers, that is, a small cache is placed on the client side, and a large cache is placed on the server side. The former augments a single request's scale through the prefetch mechanism, and the latter speedups data request response. Experimental results show the two-level cache structure increases the data transfer rate of the CD-ROM-mirroring server system.

本文提出了一种基于光盘镜像服务器系统的两级Cache结构,即在客户端建立一个小的Cache,通过预取机制增大一次请求的规模;同时,在服务器端设计一个大的Cache,加快数据请求的响应速度。实验证明,两级Cache结构大大提高了光盘镜像服务器系统的数据传输率。

 
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