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error correcting code
相关语句
  纠错码
    Then the redundancy techniques used for designing fault-tolerant computers are presented, which include hardware redundancy, information redundancy and time redundancy. Especially, the RAID and error correcting code technology are analyzed in detail.
    介绍了计算机容错设计所采用的硬件冗余、信息冗余和时间冗余技术,着重分析了RAID技术和纠错码技术;
短句来源
  纠错编码
    A properly designed error correcting code and interleaving can alleviate the requirements for the BER,relax the requirements for system design and quality of the components, and correct a 10 -5 raw BER to the 10 -12 level without sacrificing other system goals.
    设计恰当的纠错编码和数据交错技术可以减轻对原始误码率的要求 ,缓解对系统设计、部件质量等方面的要求 ,在不牺牲其它系统目标的情况下 ,使 10 - 5的原始误码率达到 10 - 12的最终误码率水平 .
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  error correcting code
An efficient software implementation of a forward error correcting code
      
Redéi to prove, that every perfect 1-error correcting code C of length p?+ 1 over an alphabet of cardinality p, such that C has a rank equal to p and a kernel of dimension p - 2, will be equivalent to some Hamming code H.
      
Finally, a detailed product operator description is given of recent NMR experiments which demonstrate a three-bit quantum error correcting code, using field gradients to implement a precisely-known decoherence model.
      
We note that this construction results in a quantum error-correcting code that corrects any n 1 errors.
      
With a powerful error-correcting code, we expect this number to increase.
      
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In this paper, we present the design and implementation by CMOS gate arrays of error detection and correction units of fault-tolerant memory systems. Two kinds of units, corresponding to two kinds of error correcting codes——odd weight code (single bit error correction and double bit error correction) and single byte error correcting Reed—Solomon Code. have been developed.The results of this research work have received complimentary approval from the Ministry of...

In this paper, we present the design and implementation by CMOS gate arrays of error detection and correction units of fault-tolerant memory systems. Two kinds of units, corresponding to two kinds of error correcting codes——odd weight code (single bit error correction and double bit error correction) and single byte error correcting Reed—Solomon Code. have been developed.The results of this research work have received complimentary approval from the Ministry of Aero-Astronautics.

本文介绍采用CMOS门阵列技术实现的、用于容错存储体的两种纠错编码电路(奇权纠错编码电路及多位纠错编码电路)的设计与实现。这两种电路均已研制成功并已通过部级鉴定。

A new kind of rate 2/3 majority logic decodable binary burst error-correcting code isconstructed using the method of majority logic decodable binary burst error-correcting codeof constructing rate 1/2. This code can correct all the error patterns with quasicyclic bursterrors whose burst error length is less than or equal to b(b=[3(m-1+h)/(12+h)],whereh=[(m-1)_12/12]).The general method for constructing this kind of error-correcting codewith a different...

A new kind of rate 2/3 majority logic decodable binary burst error-correcting code isconstructed using the method of majority logic decodable binary burst error-correcting codeof constructing rate 1/2. This code can correct all the error patterns with quasicyclic bursterrors whose burst error length is less than or equal to b(b=[3(m-1+h)/(12+h)],whereh=[(m-1)_12/12]).The general method for constructing this kind of error-correcting codewith a different rate is discussed.

采用构造码率为1/2的大数逻辑可译二进制突发错误纠错码的方法,提出了构造码率为2/3的(3m,2m)大数逻辑可译二进制突发错误纠错码,该码能够纠正所有长度小于等于b(6=[3(m-1+h)/(12+h)],其中h=[(m-1)12/12])的闭环突发错误模式,并由此得出构造此类码的一般方法

This paper presents the optimal design for B-adjacent chip error correcting codes and its incorrect probabilty of correcting double byte errors.

给出B邻中国科学院计算技术研究所CAD实验室片错误纠错码的最佳设计,分析了其双字节错误的误纠概率,从而为码的实际应用提供了依据。

 
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