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parity checking
相关语句
  奇偶校验
     Firstly, the system cannot only test rapidly for baud rate and parity checking of date, but also control input/output date flow.
     第一,它不仅能快速地进行波特率和奇偶校验的监测,而且还能控制输入输出数据流。
短句来源
     Parity checking,checksum and CRC coding are commonly used in the error detection technology.
     常用的差错检测方法通过采用奇偶校验、校验和和CRC等编码来实现;
短句来源
  “parity checking”译为未确定词的双语例句
     Parity checking is used in the two algorithms to realize the watermark embedding and blind retrieving, and the performance of the two algorithms is evaluated.
     本文在以上两种算法中均采用奇偶判别法实现水印图象的嵌入和盲提取,并对两种算法的性能进行了评测。
短句来源
     An Analysis on the Error-Correcting Effect of Multi-Dimension Parity Checking Code
     多维奇偶校验码的纠错效果分析
短句来源
     At first, the known testable design schemes of AND-OR arrays are studied and analysed, and four schemes of testable design have been gained, namely, the concurrent testable design of using special coding, the testable design of using parity checking, the testable design of signature analysis, and the divide-and-conquer testable design. At the same time the technique of boundary scan in PLDs is introduced too.
     首先从PLD的基本单元着手,研究分析了已有的关于与或阵列的可测性问题,总结出四种可测性设计方案,即使用特殊编码的并发性可测性设计,采用奇偶检测器的可测性设计,进行特征值分析的可测性设计以及分块可测性设计,并介绍了PLD中的边界扫描技术。
短句来源
     This paper presents a new conflict-free memory addressing for radix-2 FFT processor,which can read a pair of operands concurrently in one cycle. Due to no parity checking of data address the new scheme simplifies the control logic of memory banks and reduces the address generation latency of data input/output. The new approach can also be applied to radix-4 FFT processors.
     本文提出了一种新的无冲突地址生成方法,使蝶式运算单元在一个周期内能够同时读取两个操作数.由于取消了地址奇偶判别电路,简化了存储体控制逻辑,同时也加快了输入/输出地址生成.该方法还同样适用于基-4FFT处理器.
短句来源
  相似匹配句对
     Design of Totally Self-Checking Parity Logic Circuits
     全自检奇偶逻辑线路的设计
短句来源
     By checking,it is feasible.
     通过检验,证明其技术路线是可行的。
短句来源
     FACTORS AND PARITY
     因子与奇偶性
短句来源
     By checking against L. N.
     N.
短句来源
     An Analysis on the Error-Correcting Effect of Multi-Dimension Parity Checking Code
     多维奇偶校验码的纠错效果分析
短句来源
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  parity checking
The error dispersion cannot then be reduced below γ2 and it is sufficient to use in the DCC a code with parity checking (a single testing symbol; see curves 1, 2 and 3, 4 in Figs.
      
The methods for choosing the point of the recurrent measurement were tested for a nine-bit device for parity checking.
      
The second part contains the parity checking bits, which are obtained by summing over a subset of the information bits.
      
The encryption key length is 56 bits long with an additional 8 bits for parity checking.
      
Reception is based on a multi-sampling and parity checking strategy.
      
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This paper systematically describes software table algorithm for implementing polynomial error detection codes with a microprocessor.In order to speed up the implementation of polynomial error detection codes, J .S.Whiting proposed software method, but it is only suited to the case in which the number of information bits are the integral multiples of the number of the parity-check bits[1].The algorithm presented in this paper is established on the basis of J,S. Whiting's results.It applies not only...

This paper systematically describes software table algorithm for implementing polynomial error detection codes with a microprocessor.In order to speed up the implementation of polynomial error detection codes, J .S.Whiting proposed software method, but it is only suited to the case in which the number of information bits are the integral multiples of the number of the parity-check bits[1].The algorithm presented in this paper is established on the basis of J,S. Whiting's results.It applies not only to the integral multiples but also to non -integral multiples. Mathematical derivation is given in this paper, Thus the algorithm has wide-ranging adaptability .The larger the rate R of a code, the better the effect .Finally, several examples of its application are given.

本文系统地描述了在微型机上实现多项式检错码的软件表算法,把J.S.whiting提出的信息位长度是校验位的整数倍的软件表算法推广到非整数倍的更为一般的情形,给出了算法的数学推证,因此本文提出的方法具有普遍适用性。最后举例说明了这些算法的应用。

Tzeng and Zimmermann showed that the Goppa codes with L=GF(qm), g(z)=[(z-β1) (z -β2)]a (a≥1) become cyclic after being extended by an overall parity check. Recently, Tzeng and Yu showed if a = l the Goppa codes with L=GF (qm) can be extended to cyclic codes, then g(z) is quadratic. In this paper, a further necessary condition is presented. Therefore the sufficient and necessary conditions for extending Goppa codes with L = GF(qm) to cyclic codes are found.

Tzeng和Zimmermann指出,令L=CF(q~m),g(z)=[(z-β_1)(z-β_2)]~a(a≥1)的Goppa码增加一个总计校验位后可扩展成循环码。最近Tzeng和Yu又指出,当a=1时,L=GF(q~m)的Goppa码可扩展成循环码,其必要条件是g(z)为二次的。本文推广了这一必要条件,指出a为小于q~m的正整数,g(z)=[(z-β_1)(z-β_ 2)]~a。是L=GF(q~m)的Goppa码可扩展成循环码的必要条件。

The DG-1 parity check technique is described in this paper. The dynamic configuration of CPU and the structural principles of MOS memory for Hamming codes are introduced and the fault probability in CPU and MOS memory is analyzed. On this bases, the reliability of DG-1 is evaluated.

本文对DG-1型计算机的奇偶检测技术及CPU动态配置下的可靠性、可维性以及具有Hamming编码MOS存贮器的可靠性、可维性作了详细介绍和分析。文末还对DG-1的可靠性、可维性进行了简要综述。

 
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