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sub-threshold characteristics
相关语句
  亚阈值特性
     Simulation of Sub-Threshold Characteristics in Strained SiGe Channel PMOSFET
     应变SiGe沟道PMOSFET亚阈值特性模拟
短句来源
     Gate leakage current Ig,leak, threshold voltage shift, sub-threshold characteristics of nMOSFET devices with antenna ratio(AR) varying from 100 to 10 000 are analyzed to investigate the damage caused by Al etching process.
     通过分析天线比(AR)从100:1到10000:1的nMOSFET器件的栅隧穿漏电流,阈值Vt漂移,亚阈值特性来研究由Al刻蚀工艺导致的损伤。
短句来源
     Sub-threshold characteristics of strained SiGe PMOSFETs and Si PMOSFETs are theoretically analyzed with simplified models, then are simulated and compared by using a two-dimensional simulator, Medici.
     通过简化的模型,对应变SiGe沟道PMOSFET及SiPMOSFET的亚阈值特性作出了简单的理论分析,然后用二维模拟器Medici进行了模拟和对比;
短句来源
     Experiment results show that no damage antenna scale dependent is found in Vt shift while corresponding plasma charging damage is detected in gate leakage current Ig,leak and sub-threshold characteristics at low drain electric field in nMOS devices of different antenna ratio(AR).
     试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤,而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。
短句来源
     SOI-DTMOS has a better sub-threshold characteristics,much smaller sub-threshold leakage current,and thus lower static power.
     SOI DTMOS器件具有更好的亚阈值特性 ,其亚阈值泄漏电流比常规SOI器件小 2~ 3个数量级 ,从而使其具有更低的静态功耗 .
短句来源
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  相似匹配句对
     Simulation of Sub-Threshold Characteristics in Strained SiGe Channel PMOSFET
     应变SiGe沟道PMOSFET亚阈值特性模拟
短句来源
     The characteristics of G.
     论文首先对语音编码的各种方案进行了比较,并对G.
短句来源
     And the characteristics of the G.
     通过仿真和实验,也验证了G.
短句来源
     A study of threshold-voltage characteristics for deep sub-micron SOI MOSFET
     深亚微米SOIMOSFET阈值电压特性研究
短句来源
     I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.
     研究了 FINFET的 I- V特性、亚阈值特性、短沟道效应等 .
短句来源
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Based on the hydrodynamic energy transport model,the influence of variation of negative junction depth caused by concave depth on the characteristics of deep-sub-micron PMOSFET has been studied.The results are explained by the interior physical mechanism and compared with that caused by the source/drain depth.Research results indicate that with the increase of negative junction depth(due to the increase of groove depth),the threshold voltage increases,the sub-threshold characteristics and the drain current...

Based on the hydrodynamic energy transport model,the influence of variation of negative junction depth caused by concave depth on the characteristics of deep-sub-micron PMOSFET has been studied.The results are explained by the interior physical mechanism and compared with that caused by the source/drain depth.Research results indicate that with the increase of negative junction depth(due to the increase of groove depth),the threshold voltage increases,the sub-threshold characteristics and the drain current driving capability degrade,and the hot carrier immunity becomes better in deep-sub-micron PMOSFET.The short-channel-effect suppression and hot-carrier-effect immunity are better,while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source/drain junction shallow.So the variation of concave depth is of great advantage to improve the characteristics of grooved-gate MOSFET.

基于能量输运模型对由凹槽深度改变引起的负结深的变化对深亚微米槽栅 PMOSFET性能的影响进行了分析 ,对所得结果从器件内部物理机制上进行了讨论 ,最后与由漏源结深变化导致的负结深的改变对器件特性的影响进行了对比 .研究结果表明随着负结深 (凹槽深度 )的增大 ,槽栅器件的阈值电压升高 ,亚阈斜率退化 ,漏极驱动能力减弱 ,器件短沟道效应的抑制更为有效 ,抗热载流子性能的提高较大 ,且器件的漏极驱动能力的退化要比改变结深小 .因此 ,改变槽深加大负结深更有利于器件性能的提高 .

An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.

采用三维模拟软件对具有 FINFET结构的 SOI- MOSFET进行了模拟 .研究了 FINFET的 I- V特性、亚阈值特性、短沟道效应等 .模拟发现 ,通过降低 fin的高度可以有效地抑制短沟道效应与提高器件的性能 ,因此 fin的高度是器件设计中一个关键参数 .模拟结果表明 FINFET在特性上优于传统的单栅器件 .

A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics...

A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性

 
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