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rtl description
相关语句
  rtl描述
     A RTL DESCRIPTION FOR THE FINITE AUTOMATON M
     有限自动机M的RTL描述
短句来源
     On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
     文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
     On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
     在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
     If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up.
     如果存在这样的转换工具,对于使用Stateflow设计的控制逻辑部分,系统工程师可以直接向IC工程师提供系统的RTL描述,省去了IC工程师在硬件描述语言上的编程工作,使得他能够将更多的精力放在后续的设计中。
短句来源
     By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.
     提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 . 此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径
短句来源
  rtl描述的
     AN EFFECTIVE LOGIC TRANSFORM FOR THE FINITE AUTOMATON RTL DESCRIPTION
     有限自动机RTL描述的一种有效逻辑转换
短句来源
     On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
     文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
     On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
     在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
  “rtl description”译为未确定词的双语例句
     This paper analyzes structural characteristics of signal vectors in combinationalcircuits with RTL description. Then, this paper presents the concept of the BasicSimilar Circuit (BSC), a circuit constructed by compressing the bit-width of vectoredvectors in the original circuit.
     在RTL组合电路结构分析的基础上,本文提出了基本相似电路(BSC,BasicSimilar Circuit)的概念,BSC是通过对电路中信号线矢量位宽的压缩而构造的电路,缩小了电路规模。
短句来源
     Finally, we finish the whole design including RTL description, simulation, synthesis, verification and physical design in CSMC 0.5um process. The simulation frequency is up to 65MHz.
     最后基于CSMC 0.5um工艺完成了整个芯片的逻辑综合、布局布线、版图设计和验证,芯片后仿真时工作频率可以达到65MHz。
短句来源
     With cell extracted from the algorithm, a kind of cell group structure is put forward to establish exception/interrupt management unit (EIMU). The VHDL RTL description for EIMU and the algorithm is synthesized and simulated in MENTOR GRAPHICS and its simulation proves its validity.
     系统评价了任务门,中断门/陷阱门区别及优缺点.最后用EDA 工具MENTOR GRAPHICS对异常与中断管理单元及其算法的RTL级VHDL描述进行综合与仿真,验证了其正确性与有效性
短句来源
     The prototype system has been applied to verify RTL description of a real 32-bit microprocessor design and complex bugs remained hidden in the RTL descriptions are detected.
     将该方法的原型系统用于一个 32位微处理器核RTL级验证 ,发现了RTL级设计描述中的错误 .
短句来源
     The design realization is based on system design scheme,carrying on a series of processing flow,it includes RTL description,function simulation,logic synthesis,gatelevel simulation before place and routing,fit(place and routing),timing simulation,timing analysis,device programming and system verification,finally completing FPGA design.
     设计实现是以系统方案为输入,进行RTL级描述、功能仿真、逻辑综合、布线前门级仿真、适配、时序仿真、时序分析、器件编程、系统验证一系列流程的处理才能完成FPGA芯片的设计。
短句来源
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  rtl description
The need to inject faults on implicit variables of the RTL description is analyzed.
      
Verisym symbolically simulates the execution of a circuit, given as either a transistor-level schematic or an RTL description, to check a property, given as the stimulus to the circuit and the expected response.
      
When system level construction and simulation is done, a synthesis tool automatically generates RTL description.
      
The initial RTL description satis es the constraint of three adders and two counters.
      
The distinction between the RTL description and the gate-level description of a design is an important one.
      
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After definition and data structure in exception/interrupt management are analyzed, an algorithm is given to deal with the exception/interrupt.In the algorithm there are two mechanisms to answer exception/interrupt: one is to utilize a trap/interrupt gate in current task, the other is to utilize a task gate in another task. As a results, exception or interrupt which can not be processed in current task may use task gate to handle in another task. On the other hand, a basic test unit cell is deduced to generate...

After definition and data structure in exception/interrupt management are analyzed, an algorithm is given to deal with the exception/interrupt.In the algorithm there are two mechanisms to answer exception/interrupt: one is to utilize a trap/interrupt gate in current task, the other is to utilize a task gate in another task. As a results, exception or interrupt which can not be processed in current task may use task gate to handle in another task. On the other hand, a basic test unit cell is deduced to generate Boolean value for cell test to control branch in the microprogram. With cell extracted from the algorithm, a kind of cell group structure is put forward to establish exception/interrupt management unit (EIMU). The VHDL RTL description for EIMU and the algorithm is synthesized and simulated in MENTOR GRAPHICS and its simulation proves its validity.

保护方式下的异常与中断管理是微处理器设计的重要组成部分.文中探讨了异常与中断的数据结构、定义、表,给出了保护方式下的异常与中断管理算法;提出了异常/中断管理单元(EIMU)的细胞群结构,并指出细胞是异常/中断管理单元的基本测试单位;系统评价了任务门,中断门/陷阱门区别及优缺点.最后用EDA 工具MENTOR GRAPHICS对异常与中断管理单元及其算法的RTL级VHDL描述进行综合与仿真,验证了其正确性与有效性

Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis. By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.

讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径

A Verilog HDL compiler for ISCAS85/89 Benchmarks as a utility for the study of RTL combinational circuits is introduced.On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.

设计了一个针对 ISCAS 85/89Benchmark,用于 RTL组合电路 Verilog HDL描述的编译器。这个编译器可以作为 RTL电路测试研究的辅助工具。在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。

 
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