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rtl description    
相关语句
  rtl描述
    On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
    文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
    On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
    在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
    If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up.
    如果存在这样的转换工具,对于使用Stateflow设计的控制逻辑部分,系统工程师可以直接向IC工程师提供系统的RTL描述,省去了IC工程师在硬件描述语言上的编程工作,使得他能够将更多的精力放在后续的设计中。
短句来源
  rtl描述的
    On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
    文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
    On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
    在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
  RTL描述
    On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
    文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
    On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
    在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
    If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up.
    如果存在这样的转换工具,对于使用Stateflow设计的控制逻辑部分,系统工程师可以直接向IC工程师提供系统的RTL描述,省去了IC工程师在硬件描述语言上的编程工作,使得他能够将更多的精力放在后续的设计中。
短句来源
  RTL描述
    On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
    文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
    On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
    在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
    If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up.
    如果存在这样的转换工具,对于使用Stateflow设计的控制逻辑部分,系统工程师可以直接向IC工程师提供系统的RTL描述,省去了IC工程师在硬件描述语言上的编程工作,使得他能够将更多的精力放在后续的设计中。
短句来源
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  rtl description
The need to inject faults on implicit variables of the RTL description is analyzed.
      
Verisym symbolically simulates the execution of a circuit, given as either a transistor-level schematic or an RTL description, to check a property, given as the stimulus to the circuit and the expected response.
      
When system level construction and simulation is done, a synthesis tool automatically generates RTL description.
      
The initial RTL description satis es the constraint of three adders and two counters.
      
The distinction between the RTL description and the gate-level description of a design is an important one.
      
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A Verilog HDL compiler for ISCAS85/89 Benchmarks as a utility for the study of RTL combinational circuits is introduced.On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.

设计了一个针对 ISCAS 85/89Benchmark,用于 RTL组合电路 Verilog HDL描述的编译器。这个编译器可以作为 RTL电路测试研究的辅助工具。在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。

Sequential logic synthesis is an important part of RTL synthesis system design. This paper discusses sequential logic synthesis systematically. On the basis of analyzing the format of RTL descriptions written by users, it presents a synthesis method which can synthesize both basic sequential logic circuits and complex sequential logic circuits which some other systems do not introduce, at the end of this paper, it shows some concrete examples.

时序逻辑综合是 RTL综合系统设计中的一个重要部分。文章系统地论述了时序逻辑综合问题,在分析用户的 RTL描述形式的基础上,以具体算法的形式,提出基本时序逻辑电路描述综合的实现方法,同时对其它一些综合系统中未引用的复杂时序逻辑电路也提出了具体的综合实现方法。

A novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving is presented. The method only generates constraints for condition expression of the control statements, which can reduce the costs on constraint solving. It can deal with all constraints involving bits, bit-vectors and integers. It can deal with various HDL description styles, and various types of designs. Experimental results on several practical designs show that our method...

A novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving is presented. The method only generates constraints for condition expression of the control statements, which can reduce the costs on constraint solving. It can deal with all constraints involving bits, bit-vectors and integers. It can deal with various HDL description styles, and various types of designs. Experimental results on several practical designs show that our method can efficiently improve the simulation vector generation process, which in turn accelerates the design process. The vectors generated by our method can also be used in low-level verification and fault simulation. The prototype system has been applied to verify RTL description of a real 32-bit microprocessor design and complex bugs remained hidden in the RTL descriptions are detected.

提出和实现了一种面向HDL描述基于路径覆盖的模拟矢量自动生成方法 .该方法在约束生成时只考虑控制语句的条件表达式 ,可有效避免生成冗余约束 ;利用扩展的决策图模型解决了中间信号到初始输入的传播问题和信号依赖关系问题 ,以及处理各种HDL描述风格的问题 ;采用约束逻辑编程方法解决了由位、位向量和整型变量组成的约束系统的统一处理问题 .实验结果表明该方法能加快模拟矢量生成速度 ,提高路径覆盖率 .生成的模拟矢量也能用于低层次设计验证和故障模拟 ,加快了设计进度 .将该方法的原型系统用于一个 32位微处理器核RTL级验证 ,发现了RTL级设计描述中的错误 .

 
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