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programmable logic cell
相关语句
  可编程逻辑单元
     A High Performance Programmable Logic Cell for Datapath Application
     一种适于数据通路应用的高性能可编程逻辑单元
短句来源
     A novel 100,000-system-gate FPGA architecture FDP100K(FDP:FPGA for Data-Path) is proposed. It is designed for data-path application. The programmable logic cell for FDP100K is a new mixture logic block with LUT and MUX.
     设计研制了一款适用于数据通路的10万门容量的FPGA器件FDP100K(FDP:FPGA for Data-Path),其主要特点为:可编程逻辑单元结构不同于国际上已有的可编程逻辑单元结构,是一种新颖的基于查询表LUT和多路选择器MUX的混合结构;
短句来源
     An ELUT-Based Programmable Logic Cell
     一种基于扩展查询表的可编程逻辑单元
短句来源
  “programmable logic cell”译为未确定词的双语例句
     A Design of FPGA Programmable Logic Cell Structure
     一种FPGA新型逻辑单元结构的设计
短句来源
     This paper presents a new structure of FPGA programmable logic cell. This structure has more input and output ports including adding special fast carry logic,special cascade chain,and so on. This LC can not only implement arbitrary 4 input and partial 11input function,but also two arbitrary 3-input or partial 5-input function simultaneously.
     提出了一种FPGA可编程逻辑单元的新结构,该结构具有较多的输入端数和输出端数,并加入了专用的快速进位逻辑、专用级联链等功能,使得这种结构可用来实现任意4输入的逻辑函数和某些高达11个变量的输入函数;
短句来源
  相似匹配句对
     Programmable Logic to the Rescue-Again
     可编程逻辑解决方案再次成为关键
短句来源
     Design of Programmable Logic Parts
     可编程逻辑器件的设计
短句来源
     An ELUT-Based Programmable Logic Cell
     一种基于扩展查询表的可编程逻辑单元
短句来源
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Presents a high speed programmable logic cell for datapath,whose architecture consists of enhanced multiplexer.When the cell is configured for XOR XNOR MUX scheme,it can achieve the functions such as one bit full adder and base multiplier cell and so on for datapath application.It is also configured for all 3 input logic and some logic between 4 and 7 input,and used for general combinational logic.The cell is only made up of three 2:1 MUX and two enhanced 2:1 MUX...

Presents a high speed programmable logic cell for datapath,whose architecture consists of enhanced multiplexer.When the cell is configured for XOR XNOR MUX scheme,it can achieve the functions such as one bit full adder and base multiplier cell and so on for datapath application.It is also configured for all 3 input logic and some logic between 4 and 7 input,and used for general combinational logic.The cell is only made up of three 2:1 MUX and two enhanced 2:1 MUX inverted by programming,achieves fast speed and costs little chip area.The advantages of its speed and area are proved by simulation analysis with HSPICE.The larger propagating delay is less than 0 6ns and the carry chain delay is less than 0 1ns under 5V,0 6μs CMOS process.

本文提出了一种适于数据通路应用的快速可编程逻辑单元 .该单元采用功能增强的MUX结构 ,在配置为异或 同或 多路选择器 (XOR XNOR MUX)结构时 ,只用一个单元的开销就可实现一位全加器、基本乘法单元等适于数据通路应用的功能 .该单元还能实现全部 3输入逻辑和部分 4~ 7输入逻辑 ,也是一种满足通用逻辑应用的结构 .这种单元的组合逻辑部分只采用了 3个 2选 1多路选择器 (2 :1MUX)和两个功能增强的输入可反相编程的多路选择器(2 :1EMUX) ,有效地节省面积和提高了速度 .HSPICE模拟分析表明 ,在 5V、0 6 μm工艺条件下 ,该单元的最大时延小于0 6ns,进位时延小于 0 1ns.其性能、速度和面积优势非常明显

Programmable Logic Cells (LCs) play an important role in Field Programmable Gate Array (FPGA). Its performance will influence the whole performance of FPGA. So LC and the design method of its architecture is the important content in FPGA research. In this paper, n-input Look-Up Table (n-LUT) is expanded to be an Extended LUT (ELUT) by Shannon formula. The ELUT can not only implement all n-input functions, but also realize partial (n+1)~(2n-1) input functions. Thus the capacity of implementing function...

Programmable Logic Cells (LCs) play an important role in Field Programmable Gate Array (FPGA). Its performance will influence the whole performance of FPGA. So LC and the design method of its architecture is the important content in FPGA research. In this paper, n-input Look-Up Table (n-LUT) is expanded to be an Extended LUT (ELUT) by Shannon formula. The ELUT can not only implement all n-input functions, but also realize partial (n+1)~(2n-1) input functions. Thus the capacity of implementing function is enhanced under the condition of not increasing MOS transistor. By these characteristics, one 3-LUT is expanded to be 7-ELUT by Shannon formula. Then an ELUT-based LC architecture is presented by function enhancement and optimization based on one-bit Full Adder (FA) including adding fast carry chain, special cascade chain, and so on. The ELUT-based LC can not only implements arbitrary 3-input and partial 7-input function, but also realizes fast arithmetic and high fan input logic function. The LC is consists of the ELUT-based combination logic, sequence logic, cascade logic, etc. Besides general combination logic, the LCs can also implement fast datapath application logics availably such as fast full adder, multiplier, shifter and so on with fast carry chains. In additional, two cascade logics in the LC can support fast high fan logic function effectively so as to support implementing general combination logic and Finite State Machine (FSM) well. By compared with existing commercial FPGA, the LC occupies little chip area and is less MOS transistors. FPGA, be made up of the LC, can economize 40% MOS transistors compared with commercial FPGA when some important logic including datapath application logics are implemented. And one of the LCs is less than a 4-LUT too. Otherwise, the LC has favorable expansibility, regular architecture, and can be mapped easily with CAD tools. The experiments show that the LC architecture has excellent capacity of implementing function, and fast logic speed.

 通过把 3输入查询表 ,展开为 7输入扩展查询表 ,提出了一种基于扩展查询表的可编程逻辑单元新结构 .通过对扩展查询表进行功能扩展和优化 ,并加入专用快速进位链、专用级联链等功能 ,使得该结构不仅可实现任意3输入 ,部分 4~ 7输入函数 ,而且也能实现快速的算术及高扇入的逻辑 .整个单元组合部分的元件开销小于一个 4输入的查询表 .与相关商用FPGA单元结构进行的比较表明 ,该文提出的单元结构不仅占用的芯片面积较小 ,而且在速度和逻辑实现的能力上都有较大的优势 .

This paper presents a new structure of FPGA programmable logic cell.This structure has more input and output ports including adding special fast carry logic,special cascade chain,and so on.This LC can not only implement arbitrary 4 input and partial 11input function,but also two arbitrary 3-input or partial 5-input function simultaneously.And it can realize fast carry arithmetic and high fan input logic function.By comparing with existing commercial FPGA logic cell,designed LC not...

This paper presents a new structure of FPGA programmable logic cell.This structure has more input and output ports including adding special fast carry logic,special cascade chain,and so on.This LC can not only implement arbitrary 4 input and partial 11input function,but also two arbitrary 3-input or partial 5-input function simultaneously.And it can realize fast carry arithmetic and high fan input logic function.By comparing with existing commercial FPGA logic cell,designed LC not only have high resource utilization ratio,but also excellent capacity of implementing function and high performance.

提出了一种FPGA可编程逻辑单元的新结构,该结构具有较多的输入端数和输出端数,并加入了专用的快速进位逻辑、专用级联链等功能,使得这种结构可用来实现任意4输入的逻辑函数和某些高达11个变量的输入函数;这种结构还可同时实现两个任意3输入的逻辑函数或最多5输入的某些函数,而且也能实现快速的进位计算和高扇入的逻辑运算。与目前一些商业FPGA的逻辑结构进行比较表明,本文提出的单元结构不仅具有较高的资源利用率,而且在性能和函数实现能力上都有较大的优势。

 
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