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logic synthesis
相关语句
  逻辑综合
     Finally, the logic synthesis and timing analysis are implemented on the SIE in QuartusII software with FPGA Stratix serial chip EP1S10F484C5 of Altera company, and the synthesized circuit diagrams are given.
     最后,采用QuartusⅡ软件,对本文所设计的主机端串行接口引擎SIE,基于Altera公司的Stratix系列EP1S10F484C5芯片,进行逻辑综合和时序分析,并给出综合后电路图。
短句来源
     VHDL Logic Synthesis and FPGA Implementation
     VHDL逻辑综合及FPGA实现
短句来源
     An Intelligent Automatic Logic Synthesis System KDLS
     智能式自动逻辑综合系统KDLS
短句来源
     Algorithm of Decision for Analysis on Logic Synthesis on Data
     数据的逻辑综合分析及决策算法
短句来源
     Study of Based on the Threshold Gate Network for Logic Synthesis
     基于阈门网络的逻辑综合问题研究
短句来源
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  “logic synthesis”译为未确定词的双语例句
     18 μm standard cell library, the single PE will take anarea of 0.213 mm2 and can run at 350 MHz, while the logic synthesis tool used is DesignCompiler from Synopsys.
     18μm标准单元库进行实现,综合后频率可达350 MHz,占用面积为0.213 mm2。
短句来源
     1.The thesis designs an IIS (Inter-IC Sound) IP, which introduces IIS interface bus and its protocol in detail and performs RTL level simulation and logic synthesis.
     1.论文设计了一个IP软核——IIS(Inter-IC Sound)接口电路。 文中详细地讨论了IIS接口电路的总线、内侧协议、RTL(Register Transfer Level)设计、RTL级仿真和综合。
短句来源
     The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
     CPU内核采用VHDL硬件描述语言输入,结合流行的EDA设计、综合、仿真工具,最后在FPGA上实现该内核。
短句来源
     The software automatically completed the VHDL resource program analysis, logic synthesis, optimization and device programming, including logic simulation and timing simulation.
     软件自动完成VHDL源程序的分析、综合、优化及硬件下载,并对设计进行了逻辑仿真与时序仿真。
短句来源
     TIMING OPTIMIZATION IN AUTOMATIC LOGIC SYNTHESIS
     逻辑自动综合中的时间优化
短句来源
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  相似匹配句对
     AUTOMATIC LOGIC SYNTHESIS
     自动逻辑综合
短句来源
     Synthesis of p
     对氯苯甲醛的合成
短句来源
     Retiming in Logic Synthesis of ASIC
     ASIC逻辑综合中重定时序
短句来源
     Synthesis of Temoporfin
     替莫泊芬的合成
短句来源
     Logic and Pragmatics
     逻辑学和语用学
短句来源
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  logic synthesis
Our design methodology is supported by a tool that automatically generates the circuitry for the given regular expressions and outputs Hardware Description Language representations ready for logic synthesis.
      
Algebraic techniques are established in multi-level logic synthesis for the minimization of the number of literals and hence gates to implement Boolean logic.
      
The architecture was implemented using register-transfer-level VHDL description and logic synthesis with standard cells.
      
The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 μm standard cell library.
      
Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis.
      
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A procedure is presented for logic syntheses of programmable logic arrays in this paper. Problem of optimizing synthesis as wellasmethod reducing both number of input and number of product terms to be involved in this procedure.

本文提出一种可编逻辑阵列的综合方法,其中除包括输入数和积项数的减少方法以外,还讨论了逻辑综合的优化问题。

This article perfects and develops the theory and algorithm of output consistent substitution property partition further.Meanwhile it has derived a new fast iterative algorithm to simplify sequential machine,which is much more efficient and powerful than other existing ones.The program of this algorithm has been a part of software package of practical logic synthesis.

时序机状态化简是逻辑综合中必不可少的一环。有关这个课题的文献虽然不少,然而由于受传统的方法所限,距离实用化程度还有一定距离。本文的贡献在于:完善和拓广了输出一致替换性划分的理论和算法,在此基础上,推导出一种化简时序机的快迅迭代新方法。其相应的程序有较高的效率和较大的解题能力,经过十几个典型例题的验证及用随机数生成的状态表(已达到128个状态)考验,其结果的可行性、内存和机时的经济性都是较为满意的,比起目前其它方法有一定优越性,该程序已作为实用化逻辑综合软件包的一部分。

This paper describes the partitioning of the set pf the Boolean equations generated by the hardware logic translator and the conversion of the subset into cube arrays. Subsequent to this, it is aimed (1) to find the minimal sets of input variables (to eliminate redundance of input variables); (2) to finish the logic minimization; and (3) to divide a large logic array inte smaller ones, if it is needed to meet the design constraints.The three problems can all be reduced to solving the corresponding covering problems,...

This paper describes the partitioning of the set pf the Boolean equations generated by the hardware logic translator and the conversion of the subset into cube arrays. Subsequent to this, it is aimed (1) to find the minimal sets of input variables (to eliminate redundance of input variables); (2) to finish the logic minimization; and (3) to divide a large logic array inte smaller ones, if it is needed to meet the design constraints.The three problems can all be reduced to solving the corresponding covering problems, which may have considerable scales. This paper gives the method to solve the larger cycling cover tables of these problems with cover-matrix complementation (sharp operation). The salient feature of the method is that it can give the optimal solutions and need not store the covering matrix at all.The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.

本文阐明将硬件逻辑翻译器产生的布尔方程集合划分成子集后,转换成多维体列阵。然后,首先寻求输入变量最小集(消去冗余输入变量),再进行逻辑最小化,并且如果必要还可将一个较大的逻辑列阵分解成较小的列阵,以满足工程设计的约束条件。 上述三个问题都可归结为求解覆盖问题,并且其规模可能很大。本文给出用覆盖矩阵取补(锐积运算)法求解这些问题的大循环覆盖表的方法。其特点是完全不存储覆盖矩阵,可以很快给出最佳解。 上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。

 
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