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rtl synthesis
相关语句
  rtl综合
     Study On a High-Level Synthesis-Based RTL Synthesis Object and Its Methods
     基于高级综合的RTL综合对象及方法的研究
短句来源
     Format Discriminant in RTL Synthesis
     RTL综合中的格式判别
短句来源
     VHDL Arithmetic Operator Synthesis in RTL Synthesis
     RTL综合中VHDL算术操作符的综合
短句来源
     RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language).
     实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .
短句来源
     Reuse of the Controler Synthesis Technology in the Implementation of RTL Synthesis
     重用控制器综合技术实现RTL综合
短句来源
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  “rtl synthesis”译为未确定词的双语例句
     Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
     由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .
短句来源
     As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
     寄存器传输级 (RTL)综合实现从 RTL 行为描述到门级结构描述的转换 ,是目前 EDA设计行业的主流设计方法 .
短句来源
     Memory Mapping Algorithms in RTL Synthesis
     RT级综合中存储器工艺映射算法的研究
短句来源
     The base of RTL synthesis is format discriminance — distinguish combinational logic and sequential logic from behavior description, so as to use combinational logic synthesis and sequential logic synthesis separately to implement RTL synthesis.
     设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .
短句来源
     For Example, Catapult synthesis can rapidly explore multiple architectures to quickly find the best implementation for performance, area and power in FIR implementation, and make the true IP reuse possible. It also provides the area、delay and throughput(36、3、1 clock cycles) under the different constraints by table and graphics, and integrates the verification and RTL synthesis flow, so that it will improve the design efficient greatly。
     本文以FIR的实现为例,利用Catapult Synthesis快速探索不同的设计架构,快速地找到性能、面积和功耗之间折衷的最佳实现方案,使得真正的IP复用成为可能,并以图表方式给出不同约束下的面积、延迟和吞吐率(36、3、1时钟周期)的性能,同时提供了集成的验证和综合流程,极大地提高了设计效率。
短句来源
  相似匹配句对
     Format Discriminant in RTL Synthesis
     RTL综合中的格式判别
短句来源
     Synthesis of p
     对氯苯甲醛的合成
短句来源
     Memory Mapping Algorithms in RTL Synthesis
     RT级综合中存储器工艺映射算法的研究
短句来源
     The result of the RTL
     最终的RTL仿真结果表明,
短句来源
     Synthesis of Lactitol
     拉克替醇的合成
短句来源
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  rtl synthesis
We should note that Synopsys are working to improve those results, but in the meantime we recommend on the SystemC RTL synthesis flow.
      
The results of the behavioral synthesis are inferior in area and timing aspect to the RTL synthesis results.
      
The purpose of this project is to develop a modelling style that supports latch-based design and to evaluate its suitability for RTL synthesis tools.
      
The key is knowledge-based synthesis tailored to the RTL synthesis tool.
      
RTL Synthesis then passes all of these design constraints to the floorplanning environment.
      
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High level synthesis and RTL synthesis are rapidly developed technologies in electronic design automation (EDA), and retiming is an important method for optimizing design in the back of RTL synthesis. Design and implementation of the software HTC for timing correction based on retiming are introduced in the paper , and some novel algorithms are proposed. These algorithms are approximately optimal methods based on retiming and linear computing complexity, compared with the original retiming...

High level synthesis and RTL synthesis are rapidly developed technologies in electronic design automation (EDA), and retiming is an important method for optimizing design in the back of RTL synthesis. Design and implementation of the software HTC for timing correction based on retiming are introduced in the paper , and some novel algorithms are proposed. These algorithms are approximately optimal methods based on retiming and linear computing complexity, compared with the original retiming algorithm which is optimal and of high computing complexity. The software HTC is tested with a lot of examples and compared with BRT(behavioral retiming) in behavioral compiler of Synopsys, and it is shown that the two tools can achieve the same optimal goal.

高层次综合是近年来电子设计自动化(EDA)领域中快速发展的一种技术,时序重构是高层次综合后端一种重要优化方法.文中介绍了基于时序重构的时序调整软件HTC的设计与实现,提出了时序调整软件HTC中的主要优化算法,此算法与以前严格优化的计算时间复杂性较高的时序重构算法比较,是一种计算时间复杂性为线性的近似优化算法.最后给出了时序调整软件HTC的电路实例测试结果,并与商用Synopsys公司的BRT(behavioralretiming)工具进行了比较,结果表明时序调整软件HTC与上述BRT工具的优化结果相同.

According to a comparison between the RTL synthesis and high level synthesis in the aspects of the object to be processed, task to be implemented and implementation scenario, the paper explains the method of RTL synthesis. At the same time, it shows that the techniques of RTL synthesis and high level synthesis can be referred to each other. Some experimental results of RTL synthesis and high level synthesis are given.

从处理对象、任务以及实现方案等方面对不同层次上的 RTL综合及高级综合作全面比较 ,以此说明 RTL综合的对象与方法 ,同时针对这两个层次的综合实现方案 ,说明两者间可相互借鉴的技术 .最后给出了 RTL综合与高级综合的实验结果 .

Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis. By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.

讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径

 
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