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rtl synthesis
相关语句
  rtl综合
    Study On a High-Level Synthesis-Based RTL Synthesis Object and Its Methods
    基于高级综合的RTL综合对象及方法的研究
短句来源
    Format Discriminant in RTL Synthesis
    RTL综合中的格式判别
短句来源
    Realization of Sequential Logic Synthesis in RTL Synthesis System Design
    RTL综合系统设计中时序逻辑综合的实现方法
短句来源
    VHDL Arithmetic Operator Synthesis in RTL Synthesis
    RTL综合中VHDL算术操作符的综合
短句来源
    Variable Assignment Statement Synthesis MVariable Assignment Statement Synthesis Method in RTL Synthesis
    RTL综合中变量赋值语句的综合方法
短句来源
更多       
  RTL综合
    Study On a High-Level Synthesis-Based RTL Synthesis Object and Its Methods
    基于高级综合的RTL综合对象及方法的研究
短句来源
    Format Discriminant in RTL Synthesis
    RTL综合中的格式判别
短句来源
    Realization of Sequential Logic Synthesis in RTL Synthesis System Design
    RTL综合系统设计中时序逻辑综合的实现方法
短句来源
    VHDL Arithmetic Operator Synthesis in RTL Synthesis
    RTL综合中VHDL算术操作符的综合
短句来源
    Variable Assignment Statement Synthesis MVariable Assignment Statement Synthesis Method in RTL Synthesis
    RTL综合中变量赋值语句的综合方法
短句来源
更多       
  “rtl synthesis”译为未确定词的双语例句
    Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
    由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .
短句来源
    As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
    寄存器传输级 (RTL)综合实现从 RTL 行为描述到门级结构描述的转换 ,是目前 EDA设计行业的主流设计方法 .
短句来源
    The base of RTL synthesis is format discriminance — distinguish combinational logic and sequential logic from behavior description, so as to use combinational logic synthesis and sequential logic synthesis separately to implement RTL synthesis.
    设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .
短句来源
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  rtl synthesis
We should note that Synopsys are working to improve those results, but in the meantime we recommend on the SystemC RTL synthesis flow.
      
The results of the behavioral synthesis are inferior in area and timing aspect to the RTL synthesis results.
      
The purpose of this project is to develop a modelling style that supports latch-based design and to evaluate its suitability for RTL synthesis tools.
      
The key is knowledge-based synthesis tailored to the RTL synthesis tool.
      
RTL Synthesis then passes all of these design constraints to the floorplanning environment.
      
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According to a comparison between the RTL synthesis and high level synthesis in the aspects of the object to be processed, task to be implemented and implementation scenario, the paper explains the method of RTL synthesis. At the same time, it shows that the techniques of RTL synthesis and high level synthesis can be referred to each other. Some experimental results of RTL synthesis and high level synthesis are given.

从处理对象、任务以及实现方案等方面对不同层次上的 RTL综合及高级综合作全面比较 ,以此说明 RTL综合的对象与方法 ,同时针对这两个层次的综合实现方案 ,说明两者间可相互借鉴的技术 .最后给出了 RTL综合与高级综合的实验结果 .

Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain. RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language). The base of RTL synthesis is format discriminance — distinguish combinational...

Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain. RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language). The base of RTL synthesis is format discriminance — distinguish combinational logic and sequential logic from behavior description, so as to use combinational logic synthesis and sequential logic synthesis separately to implement RTL synthesis. On the basis of analysis and summary of the disciplinarian of RTL behavior description and the limitation of logic synthesis, this paper discusses indispensability, feasibility, validity of format discriminance, and puts forward a simple method to implement format discriminance. This method can divide complex behavior descriptions into several assignment statement groups, using middle data format whose kernel is assignment statement and inner format (cube) accepted by logic synthesis, determine whether the entire assignment statement group is combinational logic or sequential logic on the basis of different conditions of those assignment statements in assignment statement group, and generate different level and independent function RT units. Thus we can use corresponding logic synthesis to deal with those RT units, and use combinational logic and sequential logic to implement RTL synthesis simply. At last the paper gives some examples. Through testing several examples and analyzing the results, it is confirmed that the method presented by this paper not only distinguishes combinational logic and sequential logic from behavior description, but also reuses combinational logic synthesis and sequential logic synthesis furthest. So the time used to develop RTL synthesis is reduced greatly. This method has been used in author's RTL synthesis system.

由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .在分析和总结寄存器传输级行为描述规律以及逻辑综合局限性的基础上 ,论述格式判别的必要性、可行性、有效性 ,提出一种易于实现的格式判别方法 .该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的内部格式 (多维体 ) ,将复杂的寄存器传输级行为描述分解为各个赋值语句组 ,根据赋值语句组中的各条赋值语句的条件判断此赋值语句组是组合逻辑还是时序逻辑 ,并生成不同层次、功能相对独立的 RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此 RT单元 ,从而在实现 RTL 综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用 .最后文中给出一些测试实例和结果分析 .通过测试实例和结果分析表明...

由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .在分析和总结寄存器传输级行为描述规律以及逻辑综合局限性的基础上 ,论述格式判别的必要性、可行性、有效性 ,提出一种易于实现的格式判别方法 .该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的内部格式 (多维体 ) ,将复杂的寄存器传输级行为描述分解为各个赋值语句组 ,根据赋值语句组中的各条赋值语句的条件判断此赋值语句组是组合逻辑还是时序逻辑 ,并生成不同层次、功能相对独立的 RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此 RT单元 ,从而在实现 RTL 综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用 .最后文中给出一些测试实例和结果分析 .通过测试实例和结果分析表明该文提出的方法不但有效地区分了组合逻辑和时序逻辑 ,而且由于通过对组合?

Sequential logic synthesis is an important part of RTL synthesis system design. This paper discusses sequential logic synthesis systematically. On the basis of analyzing the format of RTL descriptions written by users, it presents a synthesis method which can synthesize both basic sequential logic circuits and complex sequential logic circuits which some other systems do not introduce, at the end of this paper, it shows some concrete examples.

时序逻辑综合是 RTL综合系统设计中的一个重要部分。文章系统地论述了时序逻辑综合问题,在分析用户的 RTL描述形式的基础上,以具体算法的形式,提出基本时序逻辑电路描述综合的实现方法,同时对其它一些综合系统中未引用的复杂时序逻辑电路也提出了具体的综合实现方法。

 
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