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   rtl synthesis 在 计算机硬件技术 分类中 的翻译结果: 查询用时:0.051秒
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rtl synthesis
相关语句
  rtl综合
    Reuse of the Controler Synthesis Technology in the Implementation of RTL Synthesis
    重用控制器综合技术实现RTL综合
短句来源
    Synthesis Method of Basic Sequential Components in RTL Synthesis
    RTL综合中基本时序逻辑元件的综合方法研究
短句来源
    Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis.
    讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .
短句来源
    By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.
    提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 . 此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径
短句来源
  RTL综合
    Reuse of the Controler Synthesis Technology in the Implementation of RTL Synthesis
    重用控制器综合技术实现RTL综合
短句来源
    Synthesis Method of Basic Sequential Components in RTL Synthesis
    RTL综合中基本时序逻辑元件的综合方法研究
短句来源
    Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis.
    讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .
短句来源
    By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.
    提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 . 此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径
短句来源
  “rtl synthesis”译为未确定词的双语例句
    Memory Mapping Algorithms in RTL Synthesis
    RT级综合中存储器工艺映射算法的研究
短句来源
    For Example, Catapult synthesis can rapidly explore multiple architectures to quickly find the best implementation for performance, area and power in FIR implementation, and make the true IP reuse possible. It also provides the area、delay and throughput(36、3、1 clock cycles) under the different constraints by table and graphics, and integrates the verification and RTL synthesis flow, so that it will improve the design efficient greatly。
    本文以FIR的实现为例,利用Catapult Synthesis快速探索不同的设计架构,快速地找到性能、面积和功耗之间折衷的最佳实现方案,使得真正的IP复用成为可能,并以图表方式给出不同约束下的面积、延迟和吞吐率(36、3、1时钟周期)的性能,同时提供了集成的验证和综合流程,极大地提高了设计效率。
短句来源
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  rtl synthesis
We should note that Synopsys are working to improve those results, but in the meantime we recommend on the SystemC RTL synthesis flow.
      
The results of the behavioral synthesis are inferior in area and timing aspect to the RTL synthesis results.
      
The purpose of this project is to develop a modelling style that supports latch-based design and to evaluate its suitability for RTL synthesis tools.
      
The key is knowledge-based synthesis tailored to the RTL synthesis tool.
      
RTL Synthesis then passes all of these design constraints to the floorplanning environment.
      
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Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis. By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.

讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径

In order to meet the requirement of Time to market and function enrichment, more and more advanced design company shift to a new abstract design level for complex DSP application, i.e. from RTL to C/C++ level, to keep their leading position. Catapult Synthesis is the first to synthesize industry-standard ANSI C++, safely generating high-quality RTL 10-20x faster than hand-coded design for ASIC or FPGA. For Example, Catapult synthesis can rapidly explore multiple architectures to quickly...

In order to meet the requirement of Time to market and function enrichment, more and more advanced design company shift to a new abstract design level for complex DSP application, i.e. from RTL to C/C++ level, to keep their leading position. Catapult Synthesis is the first to synthesize industry-standard ANSI C++, safely generating high-quality RTL 10-20x faster than hand-coded design for ASIC or FPGA. For Example, Catapult synthesis can rapidly explore multiple architectures to quickly find the best implementation for performance, area and power in FIR implementation, and make the true IP reuse possible. It also provides the area、delay and throughput(36、3、1 clock cycles) under the different constraints by table and graphics, and integrates the verification and RTL synthesis flow, so that it will improve the design efficient greatly。

为了满足产品上市时间和功能丰富性的要求,越来越多的先进设计公司开始提高设计的抽象层次进行复杂的DSP硬件设计,从RTL级提高到C/C++,以保持产品的持续领先地位。Mentor Graphics的高层次综合工具(Catapult Synthesis)是第一个综合标准的ANSI C++的产品,它可无误地生成针对ASIC/FPGA的高质量RTL代码,且速度比手工编码的快10-20倍。本文以FIR的实现为例,利用Catapult Synthesis快速探索不同的设计架构,快速地找到性能、面积和功耗之间折衷的最佳实现方案,使得真正的IP复用成为可能,并以图表方式给出不同约束下的面积、延迟和吞吐率(36、3、1时钟周期)的性能,同时提供了集成的验证和综合流程,极大地提高了设计效率。

 
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