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 combinational logic circuit 组合逻辑电路(24)组合电路(0)时序逻辑电路(2)
 组合逻辑电路
 Using Java to Realize the Combinational Logic Circuit Simulation Platform 用Java实现组合逻辑电路仿真平台 短句来源 N (23,12) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-OR gates. N(23,12)是一个异步的组合逻辑电路,能用12个大数逻辑门和77个异或门电路来实现。 短句来源 The Application of Data Selector in the Combinational Logic Circuit 数据选择器在组合逻辑电路中的应用 短句来源 This paper briefly introduces the basic method of transforming data selector into combinational logic circuit of other functions. 简述了用数据选择器转换为其它功能组合逻辑电路的基本方法。 短句来源 An algorithm for generating the complete test set of each stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) single fault in a combinational logic circuit is presented. 提出一种算法，用来产生组合逻辑电路中每个“总是0”和“总是1”单故障的完全测试集。 短句来源 更多
 时序逻辑电路
 A Design for Combinational Logic Circuit Using PLA 利用PLA设计时序逻辑电路 短句来源 For C/E system, transitions are implemented by combinational logic circuit and places are implemented by sequential logic circuit. 对于Petri网中的C/E系统,变迁用组合逻辑电路实现,库所用时序逻辑电路实现; 短句来源
 组合逻辑电路设计
 APPLICATION OF DUALITY PRINCIPLE IN DESIGNING OF COMBINATIONAL LOGIC CIRCUIT 对偶原理在组合逻辑电路设计中的应用 短句来源 We investigate the characteristics of logic functions of the multiplexer and decoder which are two members in Medium Scale Integration (MSI) by some representative types of the questions and discuss the very things when we design the combinational logic circuit with MSI. 本文通过典型设计题型 ,重点探究数据选择器和译码器两类中规模集成电路 (MSI)的逻辑功能特点 ,以及应用MSI进行组合逻辑电路设计时的特殊之处 . 短句来源
 “combinational logic circuit”译为未确定词的双语例句
 A Study of the Implication and the Input of LSI Combinational Logic Circuit 大规模组合逻辑集成电路蕴含与输入的研究 短句来源 The Design of MSI Combinational Logic Circuit MSI组合逻辑设计 短句来源 Application of stuctured approach in combinational logic circuits design 结构优化设计方法在组合网络设计中的应用 短句来源 Taking the expanding of two three-bit priority encoders into one four-bit priority encoder for example and based on the traditional designing method of combinational logic circuit, the expanding functions of priority encoder are realized through the rigorous logical derivation, full use of constraint conditions and various means of logical simplification. Meanwhile, the designing methods to expand four three-bit prio- rity encoders into one five-bit priority encoder are put forward. 以 2片 3位优先编码器 (T4 14 8)扩展为 4位为例 ,依据组合电路的传统设计方法 ,通过严密的逻辑推导 ,充分利用约束条件 ,应用逻辑简化的各种手段 ,来实现优先编码器的功能扩展 ,同时给出了 4片 3位优先编码器扩展为 5位优先编码器的设计方法。 短句来源 In the proposed way for generating full sequences a combinational logic circuit derived by the generated sequence is used to get the feedback signal,which can makes the length of a period of the sequences equal to 2n. 所提出的满序列发生器设计方法则根据不同的发生序列采用相应的组合逻辑产生反馈信号,结果可使序列长度等于2n. 短句来源

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 combinational logic circuit
 The control loop is implemented as a combinational logic circuit on an field-programmable gate array. View of a multi-level combinational logic circuit as interleaved fanin/fanout trees. The next state is computed from the current state and inputs by a combinational logic circuit. The delay of the combinational logic circuit in Figure 1 depends on the current state and the value of the primary inputs. The following algorithm is used for finding an MLV for a given combinational logic circuit. 更多
 Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher. First, we find out a new and systematical approaoh to identify all hazards of a given logic circuit on the basis of "Four-Valued Logic and Star Algorithm" , then derive formalae of hazardous tests for single or multiple stuck-at faulls... Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher. First, we find out a new and systematical approaoh to identify all hazards of a given logic circuit on the basis of "Four-Valued Logic and Star Algorithm" , then derive formalae of hazardous tests for single or multiple stuck-at faulls and for bridging faults which are undetectable statically, and a number of examples are taken, 本文系统地研究了组合逻辑线路的动态测试,给出了生成一个动态可测故障以及一个冒险可测故障(静态不可测)完全测试集的方法。首先在“四值逻辑和星算法”的基础上,导出了一个识别逻辑线路所有(静态和动态)冒险的一个新的、系统的方法,然后应用获得的结果,推导了静态不可测单固定故障、多固定故障以及桥接故障的冒险测试公式,并举出了若干实例。 In this paper the dynamic behaviors for Combinational logic circuits are investigated, the algebraic structures related to various hazards are set up, a new and systematical approach to identify hazards is proposed. It not only points explicitly out all transient input assignments to make the output of the logic networks to produce static o-hazard, static 1-haz-ard, dynamic step-down hazard, and dynamic step-up hazard, but also causes the number of transient input assignments which are needed to... In this paper the dynamic behaviors for Combinational logic circuits are investigated, the algebraic structures related to various hazards are set up, a new and systematical approach to identify hazards is proposed. It not only points explicitly out all transient input assignments to make the output of the logic networks to produce static o-hazard, static 1-haz-ard, dynamic step-down hazard, and dynamic step-up hazard, but also causes the number of transient input assignments which are needed to be verified for differentiating a kind of hazard to reduce considerably. This technique could be easily implemented in a computer program. 本文研究了组合逻辑线路的动态特性,建立了与各种冒险相关联的代数结构,提出了一个识别冒险的新的、系统的方法。该方法不仅明确地指出使网络输出产生静态0—冒险,静态1—冒险,动态负跳冒险和动态正跳冒险的所有瞬变输入赋值,而且使判定一种冒险需要验证的瞬变输入赋值的数目大大减少,易于计算机程序实现。 The properties of Boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. This method is simpler and different from the traditional one. 本文利用布尔差分的性质,给出了一种不同于传统的求组合逻辑线路故障测试码的新方法,对故障测试有一定的简化作用. << 更多相关文摘
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