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combinational logic synthesis
相关语句
  组合逻辑综合
     Research and Realization of Combinational Logic Synthesis in VHDL High-Level Synthesis System
     VHDL高级综合系统中组合逻辑综合的研究与实现
短句来源
     CLES-An Expert System for Combinational Logic Synthesis
     一个组合逻辑综合专家系统的设计与实现
短句来源
     This artical describes the design and imptementation of CLES, an expert system for combinational logic synthesis. It consists of three main parts: 1. knowledge representation for combinational logic synthesis.
     本文介绍了一个组合逻辑专家系统CLES的设计与实现,它包括三个主要部分:(1)组合逻辑综合的知识表示;
短句来源
     By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.
     提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 . 此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径
短句来源
     The base of RTL synthesis is format discriminance — distinguish combinational logic and sequential logic from behavior description, so as to use combinational logic synthesis and sequential logic synthesis separately to implement RTL synthesis.
     设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .
短句来源
  “combinational logic synthesis”译为未确定词的双语例句
     RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language).
     实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .
短句来源
     In the domain of combinational logic synthesis,logic minimization plays a vital role in determining the area and performance of the synthesized circuits.
     在组合电路综合领域,逻辑最小化对电路面积及性能起到至关重要的作用。
短句来源
  相似匹配句对
     Combinational Logic
     组合逻辑
短句来源
     AUTOMATIC LOGIC SYNTHESIS
     自动逻辑综合
短句来源
     CLES-An Expert System for Combinational Logic Synthesis
     一个组合逻辑综合专家系统的设计与实现
短句来源
     VHDL Logic synthesis and implementation
     高速CCD数字相机接口设计的VHDL逻辑综合的应用
短句来源
     Synthesis of p
     对氯苯甲醛的合成
短句来源
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  combinational logic synthesis
We have developed the first secure and reliable approach for IPP of tools and designs in the combinational-logic-synthesis domain.
      
We have developed the first watermarking-based approach for IPP of tools and designs in the combinational logic synthesis domain.
      
We have developed the first approach for IPP which facilitates design watermarking at the combinational logic synthesis level.
      
We apply these results to the 3D machine combinational logic synthesis.
      
The synthesis flow which employs watermarking of combinational logic synthesis solutions encompasses several phases illustrated in Figure 3.
      
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This artical describes the design and imptementation of CLES, an expert system for combinational logic synthesis. It consists of three main parts: 1. knowledge representation for combinational logic synthesis. 2. The design of inference and matching algorithm. 3. The Support environment for CLES.

本文介绍了一个组合逻辑专家系统CLES的设计与实现,它包括三个主要部分:(1)组合逻辑综合的知识表示;(2)推理机及匹配算法的设计;(3)CLES的支撑环境。

Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis. By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.

讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径

Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain. RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language). The base of RTL synthesis is format discriminance — distinguish combinational logic...

Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain. RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language). The base of RTL synthesis is format discriminance — distinguish combinational logic and sequential logic from behavior description, so as to use combinational logic synthesis and sequential logic synthesis separately to implement RTL synthesis. On the basis of analysis and summary of the disciplinarian of RTL behavior description and the limitation of logic synthesis, this paper discusses indispensability, feasibility, validity of format discriminance, and puts forward a simple method to implement format discriminance. This method can divide complex behavior descriptions into several assignment statement groups, using middle data format whose kernel is assignment statement and inner format (cube) accepted by logic synthesis, determine whether the entire assignment statement group is combinational logic or sequential logic on the basis of different conditions of those assignment statements in assignment statement group, and generate different level and independent function RT units. Thus we can use corresponding logic synthesis to deal with those RT units, and use combinational logic and sequential logic to implement RTL synthesis simply. At last the paper gives some examples. Through testing several examples and analyzing the results, it is confirmed that the method presented by this paper not only distinguishes combinational logic and sequential logic from behavior description, but also reuses combinational logic synthesis and sequential logic synthesis furthest. So the time used to develop RTL synthesis is reduced greatly. This method has been used in author's RTL synthesis system.

由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .在分析和总结寄存器传输级行为描述规律以及逻辑综合局限性的基础上 ,论述格式判别的必要性、可行性、有效性 ,提出一种易于实现的格式判别方法 .该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的内部格式 (多维体 ) ,将复杂的寄存器传输级行为描述分解为各个赋值语句组 ,根据赋值语句组中的各条赋值语句的条件判断此赋值语句组是组合逻辑还是时序逻辑 ,并生成不同层次、功能相对独立的 RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此 RT单元 ,从而在实现 RTL 综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用 .最后文中给出一些测试实例和结果分析 .通过测试实例和结果分析表明...

由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .在分析和总结寄存器传输级行为描述规律以及逻辑综合局限性的基础上 ,论述格式判别的必要性、可行性、有效性 ,提出一种易于实现的格式判别方法 .该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的内部格式 (多维体 ) ,将复杂的寄存器传输级行为描述分解为各个赋值语句组 ,根据赋值语句组中的各条赋值语句的条件判断此赋值语句组是组合逻辑还是时序逻辑 ,并生成不同层次、功能相对独立的 RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此 RT单元 ,从而在实现 RTL 综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用 .最后文中给出一些测试实例和结果分析 .通过测试实例和结果分析表明该文提出的方法不但有效地区分了组合逻辑和时序逻辑 ,而且由于通过对组合?

 
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