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single-byte error
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     from single to unity;
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     思维单一是缺陷
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     Single-chip Multiprocessor
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Byte error correcting codes are demanded in byte-oriented systems such as main memory, data transfer path, etc.. In this paper a class of single byte error correcting double byte error detecting codes (Sb/EC Db/ED codes) generated by means of the recursive process is presented. If the byte length is b, the length of checking part of the code is m bytes, the length of information part of the code is k bytes, then the maximal code length will be n=m+k=2m-2 (2b-1+1) bytes. In case of b= 1, these...

Byte error correcting codes are demanded in byte-oriented systems such as main memory, data transfer path, etc.. In this paper a class of single byte error correcting double byte error detecting codes (Sb/EC Db/ED codes) generated by means of the recursive process is presented. If the byte length is b, the length of checking part of the code is m bytes, the length of information part of the code is k bytes, then the maximal code length will be n=m+k=2m-2 (2b-1+1) bytes. In case of b= 1, these codes are the same with the ordinary binary Hamming SBC DED codes. Furthermore, another class of Sb/EC Db/BD rotation codes is produced with a computer. The length of such a code is longer than that of the previous one as the length of the checking part is increased.

对于面向字节组织的系统,如存储器、数据传输通路等,为了提高系统可靠性,需要采用能校正字节错的纠错码。本文提出一种用递归方法形成的单字节错校正双字节错检测码(S_bEC/D_bED码)。设字节长度为b位,该代码的校验部分长度为m字节,信息部分长度为k字节,则最大代码长度为n=2~(m-2)(2~(b-1)+1)字节。在b=1的特殊情况下,即为一般二元海明SEC/DED码。此外,用计算机推导出一种S_bEC/D_bED旋转码,这种码随校验部分长度的增加,具有比前一种码更大的代码长度。

A class of minimum square matrix codes arc presented to correct and detect-single byte-error. Because the presented codes have minimum weight of check matrix, the enco-dtr and decoder and simpler and faster. Based oh the codes, a fast single byte-error correction scheme for main memory is proposed.

本文提出一类能够纠检单个字节错误的最小方阵码,码的校验矩阵的重量达到最小,从而使得编译码电路较省、速度较快。 基于最小方阵码,本文给出一种快速内存纠错方案。

In this paper, we present the design and implementation by CMOS gate arrays of error detection and correction units of fault-tolerant memory systems. Two kinds of units, corresponding to two kinds of error correcting codes——odd weight code (single bit error correction and double bit error correction) and single byte error correcting Reed—Solomon Code. have been developed.The results of this research work have received complimentary approval from the Ministry of Aero-Astronautics....

In this paper, we present the design and implementation by CMOS gate arrays of error detection and correction units of fault-tolerant memory systems. Two kinds of units, corresponding to two kinds of error correcting codes——odd weight code (single bit error correction and double bit error correction) and single byte error correcting Reed—Solomon Code. have been developed.The results of this research work have received complimentary approval from the Ministry of Aero-Astronautics.

本文介绍采用CMOS门阵列技术实现的、用于容错存储体的两种纠错编码电路(奇权纠错编码电路及多位纠错编码电路)的设计与实现。这两种电路均已研制成功并已通过部级鉴定。

 
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