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combinational logic circuits
相关语句
  组合电路
     Neural networks based test generation algorithm for combinational logic circuits
     基于神经网络的组合电路测试生成算法
短句来源
     Research on Test Technology of Combinational Logic Circuits in the Control System of Magnetic Bearings
     磁力轴承控制系统中组合电路测试技术研究
短句来源
     Study on Chaos Control and Chaotic Optimization with Its Applications in Test Generation for Combinational Logic Circuits
     混沌控制与混沌优化及其在组合电路测试生成中的应用研究
短句来源
     FAOG: An algorithm based on filter techniques and AOG for multiple error rectification in combinational logic circuits
     FAOG:基于过滤技术和AOG的组合电路多故障诊断算法
短句来源
     Research on Netlist Optimization of Asynchronous Combinational Logic Circuits
     异步组合电路网表优化的研究
短句来源
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  组合逻辑电路
     Fabricated in a CMOS/LDMOS process based on SDB/SOI substrate,the circuit contains a D/A converter,a dual-channel comparator,flip-flops,and combinational logic circuits,as well as over-frequency and over-voltage protection circuits.
     该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。
短句来源
     Discuss the way of communal technique to design combinational logic circuits
     公用技术组合逻辑电路设计方法的初步探讨
短句来源
     Research on power analysis of CMOS combinational logic circuits
     CMOS 组合逻辑电路的功耗分析研究
短句来源
     Research on Application of OBDD to Test Generation of Combinational Logic Circuits
     OBDD在组合逻辑电路测试中的应用研究
短句来源
     Simulation of Combinational Logic Circuits Based on Petri Net
     组合逻辑电路的Petri网仿真分析
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  组合逻辑
     Multi-Fault Diagnosis for Combinational Logic Circuits
     组合逻辑多故障诊断
短句来源
     This thesis introduces the application of Simulink in the teaching of the digital circuit in both theory and experiment, and concisely narrates its main properties through examples about Combinational Logic Circuits and Sequential Logic Circuits.
     本文介绍了Simulink模拟工具在数字电路理论和实验教学中的应用,通过组合逻辑、时序逻辑电路实例简述其主要特点。
短句来源
  “combinational logic circuits”译为未确定词的双语例句
     Multiple Literal - Faults in Logic Functions and a Test Generation Method for Combinational Logic Circuits
     逻辑函数的多文字故障与组合线路测试集的生成方法
短句来源
     The Methodlogy of Dynamic Testing For Combinational Logic Circuits
     组合逻辑线路动态测试方法论
短句来源
     But, the Combinational Logic Circuits possible isn't a most simple Combinational Logic Circuits.
     但是利用最简逻辑函数实现的逻辑电路却不一定是最简的逻辑电路。
短句来源
     Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher.
     本文系统地研究了组合逻辑线路的动态测试,给出了生成一个动态可测故障以及一个冒险可测故障(静态不可测)完全测试集的方法。
短句来源
     A Transition Count Testing of Multi - output Combinational Logic Circuits
     多输出电路跳变次数(TC)测试算法
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  combinational logic circuits
One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits.
      
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG
      
We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits.
      
A method for automatic design error location and correction in combinational logic circuits
      
In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits.
      
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Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher. First, we find out a new and systematical approaoh to identify all hazards of a given logic circuit on the basis of "Four-Valued Logic and Star Algorithm" , then derive formalae of hazardous tests for single or multiple stuck-at faulls...

Yhe dynamic testing of combinational logic circuits is studied systematically, and the methods to generate the complete test set of a dynamically detectable fault as well as hazardously detectable statically undetectable fault are discussed in this paher. First, we find out a new and systematical approaoh to identify all hazards of a given logic circuit on the basis of "Four-Valued Logic and Star Algorithm" , then derive formalae of hazardous tests for single or multiple stuck-at faulls and for bridging faults which are undetectable statically, and a number of examples are taken,

本文系统地研究了组合逻辑线路的动态测试,给出了生成一个动态可测故障以及一个冒险可测故障(静态不可测)完全测试集的方法。首先在“四值逻辑和星算法”的基础上,导出了一个识别逻辑线路所有(静态和动态)冒险的一个新的、系统的方法,然后应用获得的结果,推导了静态不可测单固定故障、多固定故障以及桥接故障的冒险测试公式,并举出了若干实例。

In this paper the dynamic behaviors for Combinational logic circuits are investigated, the algebraic structures related to various hazards are set up, a new and systematical approach to identify hazards is proposed. It not only points explicitly out all transient input assignments to make the output of the logic networks to produce static o-hazard, static 1-haz-ard, dynamic step-down hazard, and dynamic step-up hazard, but also causes the number of transient input assignments which are needed to...

In this paper the dynamic behaviors for Combinational logic circuits are investigated, the algebraic structures related to various hazards are set up, a new and systematical approach to identify hazards is proposed. It not only points explicitly out all transient input assignments to make the output of the logic networks to produce static o-hazard, static 1-haz-ard, dynamic step-down hazard, and dynamic step-up hazard, but also causes the number of transient input assignments which are needed to be verified for differentiating a kind of hazard to reduce considerably. This technique could be easily implemented in a computer program.

本文研究了组合逻辑线路的动态特性,建立了与各种冒险相关联的代数结构,提出了一个识别冒险的新的、系统的方法。该方法不仅明确地指出使网络输出产生静态0—冒险,静态1—冒险,动态负跳冒险和动态正跳冒险的所有瞬变输入赋值,而且使判定一种冒险需要验证的瞬变输入赋值的数目大大减少,易于计算机程序实现。

The properties of Boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. This method is simpler and different from the traditional one.

本文利用布尔差分的性质,给出了一种不同于传统的求组合逻辑线路故障测试码的新方法,对故障测试有一定的简化作用.

 
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