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test access
相关语句
  测试访问
     Test Access Mechanism for SOC
     SOC测试访问机制
短句来源
     The test access port and test logic architecture and protocol of 1149.4 and 1149.1 standards are analyzed,and behavior models for ABM and DBM are put forward.
     文章分析了1149.4和1149.1标准的测试访问端口,以及测试逻辑结构和测试协议的异同,提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型;
短句来源
     Test architecture ,test access mechanism(TAM) and core test description language of P1500 are described in detail.
     文章详细介绍了P1500的测试架构,测试访问机制TAM及核测试描述语言CTL。
短句来源
     Since JTAG/IEEE Standardization Committee proposed jointly the IEEE1149.11990 Std the standard Test Access Port and the Boundary Scan architecture ,Boundary Scan technology has developed rapidly and has been applied extensively.
     自从1990年2月JTAG与TEEE标准化委员会合作提出了“标准测试访问通道与边界扫描结构”的IEEE1149.11990标准以后,边界扫描技术得到了迅速发展和应用。
短句来源
     SOC test architecture chiefly includes the design of TAM(Test Access Mechanism) which is used to transfer test data on chip and the design of chip-level test controller which is used to control the test of the cores on chip.
     SOC测试结构主要包括用于传送片上测试数据的测试访问机制TAM以及实现对片上核测试控制的芯片级测试控制器设计。
短句来源
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  测试通路
     Optimizing Test Access Architecture by Genetic Algorithm
     用遗传算法优化测试通路结构设计
短句来源
  “test access”译为未确定词的双语例句
     In the meantime, it also discusses Test Access Machine (TAM) for SOC test and the design of JTAG controller.
     文中同时还就SOC测试TAM及JTAG主控制器的设计问题进行了探讨。
短句来源
     As is a new hardware device for network monitoring,TAP(Test Access Port) provides a method for obtaining the network traffic without disrupting the normal traffic.
     TAP(Test Access Port/Traffic Access Port)是一种新兴的用于网络监测的硬件设备,它提供了一种在不中断网络正常流量的情况下,获得网络流量的方法。
短句来源
     In the aticle, the implementation of Standard Test Access port and Boundary Scan Architecture.
     本文探讨中国电子行业标准“标准可测性总经”第一部分“标准调试存取口与边界扫描结构”在印制板级与系统级的实现问题。
短句来源
     A microprocessor based builtin test scheme for SOC is proposed,which employs transparency path test access mechanism.
     提出了一种基于片上微处理器和透明路径测试访问的SOC自测试方案。
短句来源
     Taking Atmel's high-performance MCU Atmega16L as processing core and using Philips's high speed Universal Serial Bus(USB 1.1) peripheral controller PDIUSBD12 to communicate with PC. EPM240 generates JTAG timing. Based on Test Access Port and Boundary-Scan technology, the voltage level on pin of object processor is controlled by EPM240. At last,the flash memory connecting to processor is programmed.
     在实现上,以Atmel的高性能AVR单片机ATmega16L为核心,通过Philips的USB1.1控制芯片PDIUSBD12和上位机高速传输编程数据,同时,将组织好的数据并行发送给Altera的EPM240,由其产生JTAG时序,通过TAP(TestAccessPort)与边界扫描(BoundaryScan)技术,控制目标系统上微处理器引脚信号,最后完成与数据总线相连的FLASH存储器编程。
短句来源
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  test access
This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures.
      
The use of an expanded test access model and its concurrent definition with the system test schedule makes it possible the search for a cost effective global solution.
      
The proposed approach relies on the reuse of available system resources for the definition of the test access mechanism, and for the optimization of several cost factors (area overhead, pin count, power constraints and test time).
      
The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM).
      
The present paper introduces a new strategy for testing embedded cores using Test Access Mechanism (TAM) switches.
      
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In the aticle, the implementation of Standard Test Access port and Boundary Scan Architecture. which is Part I of Chinese Electronic Industry Standard "Standard Testability Bus" at board and system levels is overviewed and investigated. A few propositions to implement and develop the Chinese Electronic Industry Standard"Standard Testability Bus" are given.

本文探讨中国电子行业标准“标准可测性总经”第一部分“标准调试存取口与边界扫描结构”在印制板级与系统级的实现问题。简述了不要针床夹具借助边界扫描测试印制板上器件间互连的方法。综述了美国相应标准IEEEStd1149.1公布前后提出和试行在印制板级和系统级实现的若干方法和方案,包括采用符合与不符合该标准的两种器件的混合型板和系统。初步探讨了实现中国电子行业标准“标准测试存取口与边界扫描结构”和开发混合型印制板与系统的测试方法与方案问题。

Higher density and finer lead pitches of modern surface mount assemblies restrict test process,and other problems still exist,such as lack of in-circuit test patterns for large lead count ASIC S、lack of test access、etc,all these factors prevent test engineers from realizing high fault coverage test.In this paper,some test techniques used currently will be discussed,include digital pattern libraries,algorithmic pattern generation,vectorless test and boundary scan,and all these techniques...

Higher density and finer lead pitches of modern surface mount assemblies restrict test process,and other problems still exist,such as lack of in-circuit test patterns for large lead count ASIC S、lack of test access、etc,all these factors prevent test engineers from realizing high fault coverage test.In this paper,some test techniques used currently will be discussed,include digital pattern libraries,algorithmic pattern generation,vectorless test and boundary scan,and all these techniques used together to optimize fault coverage.

现在的表面安装电路板密度越来越高,而且引脚间距变得越来越小,这些限制了测试工作,同时,又存在着另外一些问题,如缺少对多引脚ASICS的在线测试图形、缺少探测通道等,所有这些因素都阻碍了测试工程人员实现高缺陷覆盖率的测试工作。文中讨论的是当前使用的测试技术,包括数据图形库、算法图形生成、非向量测试和边界扫描,以及这些技术的综合使用,以实现最优的缺陷覆盖

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented...

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

IEEE1149.1边界扫描为数字电路板级测试提供了所需的对内部节点的控制和观察能力。但是,边界扫描测试结构本身的完整性必须首先加以检测,以保证其他功能测试和诊断结果的正确性。本文论述了板级边界扫描测试存取口的故障模型和测试原理,并针对全边界扫描印制板提出了一种故障覆盖率高、测试时间短的测试算法。

 
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