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   dynamic instruction 的翻译结果: 查询用时:0.191秒
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dynamic instruction
相关语句
  动态指令
     A Hardware Oriented Model for Dynamic Instruction Translation
     一种全硬件动态指令翻译模型
短句来源
     This Hope-Mips in this project provides simple function Sim-simulator, simulation super-microprocessor and architecture Sim-outorder simulator, in which the Sim-outorder simulator supports dynamic instruction dispatch, instruction our-of-order execution and branch prediction.
     Hope-Mips拥有简单的功能模拟器,同时具备模拟超标量微处理器体系结构的乱序性能模拟器,其乱序模拟器支持动态指令调度、指令乱序执行、分支预测等。
短句来源
     Specially,YH TS 1 has dynamic instruction schedule with two instruction fetch units,vector processing mechanism towards embedded application,content copy/switch based register window interrupt processing mechanism,and support of the open WISHBONE IP interface specification.
     特别的 ,TS 1具有两个取指部件的动态指令调度机制 ,拥有面向嵌入式应用的向量处理机制 ,采用基于内容复制 /交换的寄存器窗口技术的中断处理机制 ,支持WISHBONEIP核互连接口规范 ,具有良好的扩展性 .
短句来源
  “dynamic instruction”译为未确定词的双语例句
     We discuss the interactions between static and dynamic instruction scheduling and show that static instruction scheduling is beneficial even the hardware has dynamic scheduling. We also describe the framework of instruction scheduling in our compiler and present experimental results to show its performance.
     本文首先分析了硬件动态调度和静态指令调度之间的关系,说明了静态指令调度的必要性,然后介绍了指令调度在龙芯I编译器中的具体实现,最后给出了实验结果以说明指令调度的实际效果。
短句来源
     Test and performance analysis show that the dynamic instruction pipeline of the Godson 1 processor is efficient and its security design can effectively defense network attack based on buffer overflow technique.
     测试表明龙芯 1号处理器的指令流水线效率高 ,其安全设计能有效防范使用缓冲区溢出技术进行的网络攻击 .
短句来源
     Based on the study and analysis of the DAISY and the Crusoe(tm), a hardware oriented model for dynamic instruction translation is proposed.
     文章在研究分析DAISY和Cruseo(tm)这两款处理器后,针对X86指令集系统提出一种全硬件的动态翻译模型。
短句来源
  相似匹配句对
     DYNAMIC
     动态
短句来源
     Dynamic
     地方科技动态
短句来源
     A Hardware Oriented Model for Dynamic Instruction Translation
     一种全硬件动态指令翻译模型
短句来源
     Z80 INSTRUCTION SET EMULATED BY DYNAMIC GRAPH ON COMPUTER
     Z80指令系统的计算机动态图形模拟
短句来源
     On the Situationality of Instruction
     论教学的境遇性
短句来源
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  dynamic instruction
By analyzing, recording, and utilizing the key information of the dynamic instruction flow early in the front-end pipeline, CASA brings the opportunity to maximize the power efficiency and minimize the performance overhead.
      
These enhancements are aggressive dynamic (run time) instruction scheduling, the reuse of decoded instructions, and trace scheduling (both aggressive dynamic instruction scheduling and decoded instruction reuse have been used in commercial systems).
      
It incorporates procedure static and globally dynamic instruction scheduling, multiple, simultaneous branch path execution, and iteration frames for executing loops with recurrences and conditional branches.
      
Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture
      
Instruction Reuse is a microarchitectural technique that exploits dynamic instruction repetition to remove redundant computations at run-time.
      
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Student model plays a key role in the dynamic instruction process of ICAI. This paper proposes a practical student model which using fuzzy measure and its propagation within a network to depict the student's mental status and his learning ability effectively. The complexity of the model is considerablely reduced by its delay computation technique.

提出了一种实用的学生模型化方法。采用模糊测度和与之相应的网络传播算法,能准确描述学生的认知状态、学习能力和学习愿望,应用延迟计算技术,大大降低了模型的复杂度。

YH TS 1 is a 32 bit embedded microprocessor designed by School of Computer in National University of Defense Technology.It is a top down design and has fully intellectual property.YH TS 1 has a RISC core,six stage pipeline,separated data Cache and Instruction Cache.Specially,YH TS 1 has dynamic instruction schedule with two instruction fetch units,vector processing mechanism towards embedded application,content copy/switch based register window interrupt processing mechanism,and support of...

YH TS 1 is a 32 bit embedded microprocessor designed by School of Computer in National University of Defense Technology.It is a top down design and has fully intellectual property.YH TS 1 has a RISC core,six stage pipeline,separated data Cache and Instruction Cache.Specially,YH TS 1 has dynamic instruction schedule with two instruction fetch units,vector processing mechanism towards embedded application,content copy/switch based register window interrupt processing mechanism,and support of the open WISHBONE IP interface specification.This paper will mainly describe the YH TS 1 RISC core design methodology and its critical implementation technologies.The experimental results will also be given at the end of the paper.TS 1 has been implemented and verified in Altera's FPGA EP20K400EBC,and the clock frequency can be 36.7MHz.

银河TS 1嵌入式微处理器是国防科学技术大学计算机学院设计的 32位嵌入式微处理器 ,完全正向设计 ,具有自主版权 .在体系结构上采用RISC内核 ,六级流水线 ,具有独立的数据Cache和指令Cache .特别的 ,TS 1具有两个取指部件的动态指令调度机制 ,拥有面向嵌入式应用的向量处理机制 ,采用基于内容复制 /交换的寄存器窗口技术的中断处理机制 ,支持WISHBONEIP核互连接口规范 ,具有良好的扩展性 .本文主要介绍TS 1的RISC核心设计思想和关键实现技术 ,最后给出性能评测结果 .TS 1设计已经在Altera的FPGAEP2 0K4 0 0EBC上面得到了验证 ,主频可以达到 36 .7MHz.

The Godson 1 processor is a general purpose high performance processor developed in Institute of Computing Technology, Chinese Academy of Sciences. This paper first gives the background and considerations of designing the Godson series of microprocessors. It then introduces the architecture of the Godson 1 processor, including its out of order instruction pipeline, precise exception strategy, branch prediction, memory management, and security design to avoid buffer overflow attack. Test and performance...

The Godson 1 processor is a general purpose high performance processor developed in Institute of Computing Technology, Chinese Academy of Sciences. This paper first gives the background and considerations of designing the Godson series of microprocessors. It then introduces the architecture of the Godson 1 processor, including its out of order instruction pipeline, precise exception strategy, branch prediction, memory management, and security design to avoid buffer overflow attack. Test and performance analysis show that the dynamic instruction pipeline of the Godson 1 processor is efficient and its security design can effectively defense network attack based on buffer overflow technique. However, the cache of Godson 1 processor is not large enough and its organization could be improved .

首先介绍了龙芯处理器的研制背景及其技术路线 .分析了龙芯处理器坚持高性能定位、稳扎稳打的设计策略以及兼容主流处理器的原因 ,并指出在目前达到与国外相同主频的客观条件不具备的情况下 ,应走通过优化处理器结构来提高性能的道路 ,并以处理器结构技术的突破为根本 .然后介绍了龙芯 1号处理器的体系结构设计 ,包括基于操作队列复用的动态流水线设计、在乱序执行的情况下实现精确例外处理、取指与转移控制结构、存储管理以及针对缓冲区溢出攻击的系统安全设计等等 .测试表明龙芯 1号处理器的指令流水线效率高 ,其安全设计能有效防范使用缓冲区溢出技术进行的网络攻击 .但龙芯 1号处理器的Cache过小 ,在组织方式上也有待改进

 
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