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symmetric circuit
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  “symmetric circuit”译为未确定词的双语例句
     The proposed symmetry searching algorithm can find the maximal symmetry structures in a none fully symmetric circuit.
     提出的对称查找算法适用于非全对称电路的最大匹配对称结构查找 .
短句来源
  相似匹配句对
     Symmetric Copula
     具有对称性的Copula
短句来源
     FPGA circuit
     FPGA电路设计
短句来源
     On the Dynamic Circuit
     动态电路分析的几个问题
短句来源
     An Investigation on the Sampling-Holding Circuit With Symmetric Switching Capacitor
     对称开关电容采样保持电路的研究
短句来源
     Calculation of the Equivalent Circuit Parameters for the Open Resonator with Circularly Symmetric Spherical-Surfaces
     圆形对称球面开放腔等效电路参量的计算
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  symmetric circuit
On the other hand, given non-symmetric circuit matrix of a non-reciprocal circuit, the reduced circuit matrix is still not symmetric.
      
Given a reciprocal network and its symmetric circuit admittance matrix, the reduced circuit matrix is still symmetric after hierarchical reduction.
      


This paper proposes a new technique to automatically generate STACK layout for MOS analog cell circuits. The circuit net list is first mapped into a diffusion graph. Based on the diffusion graph, circuit partition, pattern recognition and symmetry searching are carried out to generate sub graphs, each of which can be implemented by a STACK. The proposed symmetry searching algorithm can find the maximal symmetry structures in a none fully symmetric circuit. To guarantee the generation of a Eularian trail,...

This paper proposes a new technique to automatically generate STACK layout for MOS analog cell circuits. The circuit net list is first mapped into a diffusion graph. Based on the diffusion graph, circuit partition, pattern recognition and symmetry searching are carried out to generate sub graphs, each of which can be implemented by a STACK. The proposed symmetry searching algorithm can find the maximal symmetry structures in a none fully symmetric circuit. To guarantee the generation of a Eularian trail, the Atallah Eularian trail generation algorithm is improved by employing the dummy adding technique. In order to evaluate the performance of a generated STACK, a distributed parasitic capacitance model is applied to calculate the STACK node parasitic capacitance, as well as the calculation of STACK area and shape.

提出了一种新的 MOS模拟单元电路的 STACK版图自动生成方法 .该方法将电路网表映射为扩散图 ,基于扩散图进行电路划分、模板匹配和对称查找 .提出的对称查找算法适用于非全对称电路的最大匹配对称结构查找 .文中改进了 Atallah欧拉路径生成算法 ,通过增加哑元条保证欧拉路径的生成 .对生成的 STACK,采用分布式寄生电容模型计算各个节点的寄生电容 ,并计算 STACK的面积和形状 ,以确保其能够满足设计要求

 
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