Seqondly, we emphasized on the architecture and working methods of Pentium processor's APIC system, and we analyzed the limitation of the APIC at the high performance microprocessors, also we introduced the Streamlined Advanced Programmable Interrupt Controller (SAPIC) system and its attribute about architecture and performance.
Compared with traditional PACS that are based on DICOM networks, distributed PACS improve themselves in system architecture and performance. However, the speciality and complexity of the DICOM standard prevent the improvements in the performance of distributed PACS.
This paper describes the design and implementation of a kind of Customer Relation management information system based on J2EE architecture, and focuses on the main functions, design principle and tactics of the system. Particularly, we adopt J2EE solution, which makes this system have better architecture and performance.
This article introduces the architecture and performance of SonyEricsson GR47 communication module , and provides a design of vehicle orientation and supervisal system based on GR47 and its application program flowchart.
According to the development status of expressway communication net work and the data transmission requirement for toll collection system, this pap e r analyzes in aspect of architecture and performance, the three network techno lo gy suitable for expressway communication: SDH, ATM and IP, and their integra ted model: ATM Over SDH, IP Over ATM, IP Over SDH, IP Over WDM.
结合目前我国高速公路通信传输网络的建设现状和收费系统数据通信的需求，从 结构、性能等方面分析了适应高速公路通信的3种网络技术SDH、ATM和宽带IP技术，以及这 3 种技术的综合集成模型ATM Over SDH、IP Over ATM、IP Over SDH、IP Over WDM。
Probing into the major network management technologies, this paper introduces a novel design of network management in relation to topology architecture, management model, management architecture and performance monitoring.
In this paper, the architecture and performance of a coherent IR receiver based on single bit quantization will be analyzed from the perspectives of Rake receiver processing, channel estimation and signal detection.
Integrated services packet networks with mobile hosts: Architecture and performance
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security
Architecture and Performance Evaluation for Redundant Multicast Transmission Supporting Adaptive QoS
The Architecture and Performance of a Stochastic Competitive Evolutionary Neural Tree Network
This paper presents the system architecture and performances of the 128-line subscriber's line concentrator controlled by the stored program. Some major technical problems encountered in the designing of the system are also described.
This paper introduces eight current micro-computer bus stansards and compares the architecture and performance ofthe buses.
This paper discusses the characteristics of single-chip programmbledigtal signal procsssor(DSP).The paper focuses on single-chip DSPs and comparestheir architecture and performance to general-purpose microprocssors and micr-ocontrollers.Available DSPs are discussed and the application trends of DSP incontrol are explored,