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clock generating circuit
相关语句
  时钟发生电路
     The signal collecting system of singlechip collects the signals from generator. The paper introduces the every part of the singlechip. The key component is a 8051CPU, its surrounding circuits include DC power source, simulating signal collecting circuit, digital signal collecting circuit, A/D converting circuit, clock generating circuit, counting frequency circuit, controlling circuit, communicating circuit, and some other circuits.
     前台单片机采集系统完成对发电机组多信息量的采集,本文详细介绍了电路设计,系统的核心器件为8051CPU,其外围电路包括电源电路、模拟信号采集电路、A/D转换电路、数字信号采集电路、时钟发生电路、测频电路、控制电路、通讯电路等。
短句来源
     In order to reduce the cost and power of the system,this paper samples the high frequency sygnal(6.25MHz~100MHz)equivalently based on the precision clock generating circuit,and designs high speed circuit,AD,FIFO and FPGA etc. and implements a portable memoryoscillograph.
     为了降低系统成本和功耗,采用基于ARM系统的精密时钟发生电路对高频信号(6.25MHz~100MHz)进行等效采样,配合高速AD、FIFO和FPGA电路设计并实现一个手持式存储示波表。
短句来源
  时钟产生电路
     Design of Clock Generating Circuit in 10-Gigabit Ethernet
     万兆以太网时钟产生电路设计
短句来源
  相似匹配句对
     Design of Clock Generating Circuit in 10-Gigabit Ethernet
     万兆以太网时钟产生电路设计
短句来源
     The True Clock Circuit and Its Applications
     真时钟电路及其应用
短句来源
     Design of high speed clock circuit
     高速时钟电路设计
短句来源
     A Real-time Pulse Generating Circuit
     一种实时脉冲信号发生电路
短句来源
     CCM and Its Generating for Analog-Digital Hybrid Circuit
     模拟数字混合电路的元件连接模型及其生成方法
短句来源
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This paper presents the design and characterization of a monolithic 10GHz frequency synthesizer/multiplier based on a 0.2μm GaAs PHEMT technology. They include system model, circuits topology, performance analyse, layout design, simulation results and process characteristic. The chip is composed of a VCO, a frequency divider, a phase detector and a low pass filter. The simulation results in ADS show that: The power consumption is 400 mW at supply voltage of 3.3V. The output power is about -15dBm. The operating...

This paper presents the design and characterization of a monolithic 10GHz frequency synthesizer/multiplier based on a 0.2μm GaAs PHEMT technology. They include system model, circuits topology, performance analyse, layout design, simulation results and process characteristic. The chip is composed of a VCO, a frequency divider, a phase detector and a low pass filter. The simulation results in ADS show that: The power consumption is 400 mW at supply voltage of 3.3V. The output power is about -15dBm. The operating frequency range covers 9.5GHz~11.0GHz. The phase noise is -95dBc/Hz@1MHz and peak to peak jitter is about 2ps. The chip size is 1 25×1 35mm 2. It can be adopted in the clock generating circuits of 10 Gigabit Ethernet.

给出了基于 0 .2 um Ga As PHEMT工艺的 10 GHz单片频率综合器的系统模型、电路结构、性能分析、版图设计以及仿真结果 ,并简单介绍了工艺特点。整个芯片由压控振荡器、分频器、鉴相器以及低通滤波器组成。在 ADS软件下的仿真结果表明 :芯片采用 3 .3 V单电源供电 ,总功耗为 40 0 m W,输出功率为 -15 d Bm,工作频率 9.5 GHz~ 11.0 GHz,相位噪声 -95 d Bc/Hz@1MHz,输出信号的峰峰值抖动约为 2 ps。整个芯片面积为 1.2 5× 1.3 5 mm2 ,适合作为万兆以太网的时钟产生电路

In order to reduce the cost and power of the system,this paper samples the high frequency sygnal(6.25MHz~100MHz)equivalently based on the precision clock generating circuit,and designs high speed circuit,AD,FIFO and FPGA etc.and implements a portable memoryoscillograph.This unit is provided with two operation modes,manual measurement and automatic measurement,for manmachine interface,which has a high cost performance and the bright future.

为了降低系统成本和功耗,采用基于ARM系统的精密时钟发生电路对高频信号(6.25MHz~100MHz)进行等效采样,配合高速AD、FIFO和FPGA电路设计并实现一个手持式存储示波表。该样机在人机界面上为用户提供了手动测量和自动测量两种工作模式,性价比高,可望有广阔的前景。

Based on the traditional phase-locked loop circuit, a high-performance inbuilt mixed-signal phase-locked loop circuit is designed. It can generate multiple rated clocks and provide a mostimportant applicable clock-generating circuit for the design of the current ASIC and SOC. Simulationresults show that the circuit has a higher output frequency of 500MHz, a smaller settling time of 700ns, a lower power consumption of 18mW at 1.8V, and the noise is less than 180mV....

Based on the traditional phase-locked loop circuit, a high-performance inbuilt mixed-signal phase-locked loop circuit is designed. It can generate multiple rated clocks and provide a mostimportant applicable clock-generating circuit for the design of the current ASIC and SOC. Simulationresults show that the circuit has a higher output frequency of 500MHz, a smaller settling time of 700ns, a lower power consumption of 18mW at 1.8V, and the noise is less than 180mV.

在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构。它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片(ASIC)和系统芯片(SOC)的实现提供最基础且最重要的可应用时钟产生电路。模拟结果表明,该锁相环可稳定输出500MHz时钟信号,稳定时间小于700ns,在1.8V电源下的功耗小于18mW,噪声小于180mV。

 
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