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We use the pipelined array multiplier as an example, and show that it is Ctestable with 214 twopattern tests.


The first set of designs include a number of pipelined array multipliers.


Since Motion Estimation is a highly parallel application it is implemented on a 16x16 pipelined array of processors.




 The term Pipelined Array Processor (PAP) used here covers a new class of array processor suitable for VLSI. In PAP, several data items flowing along different pipes may meet and interact. "We refer to this pipelining as array pipelining. The algorithms suitable for PAP, called array pipelining algorithms, are quite different from those of conventional computers. They can be directly implemented with hardware. Moreover, in PAP the data flows are highly regular, therefore, it is possible... The term Pipelined Array Processor (PAP) used here covers a new class of array processor suitable for VLSI. In PAP, several data items flowing along different pipes may meet and interact. "We refer to this pipelining as array pipelining. The algorithms suitable for PAP, called array pipelining algorithms, are quite different from those of conventional computers. They can be directly implemented with hardware. Moreover, in PAP the data flows are highly regular, therefore, it is possible to design array pipelining algorithms in a unified fashion.In this paper a class of recurrence process expressed as z(k) (i, j) = f[z(k1) (i, j), x(i,k), Y(k, j)] is investigated and would be able to implement in PAP. In order to characterize the dynamic procedure of array pipelining, we define 12 array pipelining parameters, in which three are for the speeds of data flows, six for data distributions and three for time factors. By analyzing the iterative procedure of array pipelining, a theorem of array pipelining representing the relationship among the above parameters is proposed and is expressed by six linear equations. An array pipelining scheme can be completely determined by its array pipelining parameters, therefore, with some parameters reasonablely given, the unknown parameters can be derived by solving the linear system of equations, thus an array pipelining algorithm can be obtained. We refer to this method as the parameter method for designing array pipelining algorithms. Usually, for a given problem several array pipelining algorithms can be yielded by using this parameter method. We can compare them and make an optimal choice. Various array pipelining algorithms proposed by others, such as systolic array suggested by H. T. Kung et al. can be derived conveniently by means of this parameter method.In order to show the power of this parameter method, some new array pipelining algorithms, such as for matrix multiplication, FIE filtering, DFT, triangular matrix inversion, etc., are also worked out in this paper. These algorithms are more reasonable than existing ones.  阵列流水算法是与集成电路的迅速发展相适应的高速并行算法,它可在流水式阵列处理机中直接由硬件实现。本文通过分析阵列流水的时间空间关系得出阵列流水原理,并以此原理为基础提出了设计阵列流水算法的一种统一的方法——阵列流水参数确定法。根据这个方法,处理递归问题的各种阵列流水方案可以推导出来。本文运用确定参数法设计了矩阵乘法,FIR滤波,DFT,三角形矩阵求逆等新的更合理的阵列流水算法。  A method of predistributing the calculated data by some additional judge logics is presented to optimize the power consumption of a pipelined array multiplier.Results from the experiment are compared by gatelevel simulation and registerannotated methods.It has been shown that this simple method of optimization is effective in decreasing the power consumption of the circuit.So,it can be widely used in the implementation of lowpower design of other datapath modules with asymmetric architectures and... A method of predistributing the calculated data by some additional judge logics is presented to optimize the power consumption of a pipelined array multiplier.Results from the experiment are compared by gatelevel simulation and registerannotated methods.It has been shown that this simple method of optimization is effective in decreasing the power consumption of the circuit.So,it can be widely used in the implementation of lowpower design of other datapath modules with asymmetric architectures and symmetric logic behaviors.  针对流水线结构阵列乘法器,分别采用寄存器翻转统计和门级翻转率统计的方法进行了功耗分析,创新地提出了一种通过增加判断逻辑进行数据预分流以实现功耗优化的方法。实验结果证明,这种优化方法能够带来明显的功耗节省。类似方法也可普遍用于逻辑行为对称但实现结构不对称的数据通路单元的低功耗设计实现中。  
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