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schottky device
相关语句
  肖特基器件
     Influence of Wirebonding to the Forward Voltage Drop of Schottky Device
     压焊方式对肖特基器件通态压降的影响
短句来源
     In the retral encapsulation process of semiconductor device, the different wirebonding results in different contact area between the Al and Schottky junction, and then induces different contact resistance, ultimately influences the forward voltage drop of Schottky device.
     在半导体器件的后部封装工艺中,不同的压焊方式会导致不同的铝丝和肖特基结接触面积,从而导致不同的接触电阻,最终影响肖特基器件的通态压降。
短句来源
  “schottky device”译为未确定词的双语例句
     The Schottky device with this structure was fabricated and C-V measurement was made to verify the existence of the 2DHG and the validity of calculation results.
     计算结果表明,势垒层AlGaN和顶层GaN的应变状态和厚度对极化引起的2DHG面密度及分布有重要影响.
短句来源
  相似匹配句对
     Influence of Wirebonding to the Forward Voltage Drop of Schottky Device
     压焊方式对肖特基器件通态压降的影响
短句来源
     Characteristics of Schottky Junctions Formed in Polymer Electroluminescent Device
     半导体聚合发光二极管的结特性研究
短句来源
     Schottky I~2L
     肖特基I~2L
短句来源
     Infusion device
     输血输液装置
短句来源
     The Schottky Theorem on Annulus
     圆环上的Schottky定理
短句来源
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  schottky device
Photocurrent characteristics of a double junction Au/Cu2O/Mo Schottky device
      
Si nanowires, under certain conditions show I-V characteristics of a back-to-back schottky device.
      


C-V and I-V characteristics of ultratllin metal/LB insulating films/semiconductor structure are studied. Theoretical analysis are well in accord with experimental results. The results indicate that: (1) Ultrathin MLS structure has normal C-V and I-V characteristics; (2) It is possible to modify the barrier height of Schottky devices by using LB thin films as insulators.

本文研究了超薄的金属/LB绝缘膜/半导体(MLS)结构的C-V和I-V特性,理论分析与实验结果相一致,结论如下:(1)超薄MLS结构具有正常的C-V特性和I-V特性;(2)以LB薄膜作为绝缘层可调整肖特基器件势垒高度。

The silicon technology continues to scale down in order to improve the reliability and the performance/cost of the electric system. But when the feature size of semiconductor device less than 50nm, there exist kinds of challenges coming from traditional material, device structure, process as well as conventional scaling down method. Our 973 project focus on the key problems on the novel materials, novel devices structures and novel fabricate process in sub 50nm devices. This paper is...

The silicon technology continues to scale down in order to improve the reliability and the performance/cost of the electric system. But when the feature size of semiconductor device less than 50nm, there exist kinds of challenges coming from traditional material, device structure, process as well as conventional scaling down method. Our 973 project focus on the key problems on the novel materials, novel devices structures and novel fabricate process in sub 50nm devices. This paper is the main research results on the fields of planar double gate devices, metal gate devices, DSOI devices, SON devices, SOI Schottky devices and high K dielectric devices.

为了提高系统芯片的可靠性和性能价格比,增强其市场竞争力,缩小器件特征尺寸并提高集成度仍是一个主要的途径。当器件特征尺寸进入亚50nm以后,大量来自于传统工作模式、传统材料、传统工艺乃至传统器件物理基础等方面的问题将成为器件特征尺寸进一步缩小的限制性因素。因此我们的973项目从新型材料、半导体器件分析、新型器件结构、关键制备工艺等方面开展了深入的研究。本文主要介绍我们在新型半导体器件结构以及制备工艺方面取得的主要成果,具体包括平面双栅器件、金属栅器件、垂直沟道双栅器件、DSOI器件、SON器件、SOI肖特基晶体管、高K介质器件等。

In the retral encapsulation process of semiconductor device, the different wirebonding results in different contact area between the Al and Schottky junction, and then induces different contact resistance, ultimately influences the forward voltage drop of Schottky device. According to the formula of V-I of Schottky device, we get the different contact resistance by means of curve fitting based on MATLAB. The reasonable wirebonding has been chosen through experiment in order to enhance...

In the retral encapsulation process of semiconductor device, the different wirebonding results in different contact area between the Al and Schottky junction, and then induces different contact resistance, ultimately influences the forward voltage drop of Schottky device. According to the formula of V-I of Schottky device, we get the different contact resistance by means of curve fitting based on MATLAB. The reasonable wirebonding has been chosen through experiment in order to enhance the yield of the 80CPQ020 Schottky rectifier module.

在半导体器件的后部封装工艺中,不同的压焊方式会导致不同的铝丝和肖特基结接触面积,从而导致不同的接触电阻,最终影响肖特基器件的通态压降。根据肖特基器件的电流鄄电压关系式,用MATLAB曲线拟合的方式求出了不同压焊方式下的接触电阻。通过实验选取合理的压焊方式,可极大地提高器件的合格率。

 
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