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rtl模型
相关语句
  rtl module
     RTL Module Design of Data-RAM for Floating-Point Digital Signal Processor
     浮点数字信号处理器Data-RAM的RTL模型设计
短句来源
     The design of Data-RAM on gates level and physical level can be directed by this RTL module.
     Data-RAM的RTL模型设计为门级和物理级的性能设计提供了参考.
短句来源
     Structure and accessing principles of Data-RAM are studied. By using top down method and VHDL,RTL module is designed and the correctness of function confirmed.
     分析了Data-RAM的结构和访问机制,采用自顶向下的方法和VHDL语言,实现了Data-RAM的RTL模型设计并验证了其功能的正确性.
短句来源
  “rtl模型”译为未确定词的双语例句
     Verilog RTL Model
     Verilog RTL模型
短句来源
     A register translation level(RTL) module design method of Data-RAM for double precision float-point digital signal processor is proposed.
     提出了一种双精度浮点数字信号处理器Data-RAM的RTL模型设计方法.
短句来源
     Using the VMC’s support of MIPS instruction set,and by running the assemble program for test in this environment which connects the VMC model of the MIPS processor core and the RTL model of the HDTV SoC,the software and hardware of SoC synchronously can be debuged,which can lead to a high-efficiency of SoC verification.
     连接MIPS处理器内核的VMC模型和SoC的RTL模型,利用VMC模型支持MIPS指令集的特性运行测试汇编程序,实现了SoC软硬件的同步调试,有效地提高了系统验证的效率。
短句来源
     SystemC provides a fast way to build the hardware function reference module.
     硬件参考模块模拟RTL模型的逻辑功能,在SystemC的基础上开发。
短句来源
     Then the RTL level circuit models using HDL are built;
     由EDA工具对RTL模型进行综合;
短句来源
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  相似匹配句对
     Verilog RTL Model
     Verilog RTL模型
短句来源
     This improved mixing dielectric model yields an excellent fit to measured data.
     模型
短句来源
     Obviously, EVA model turns out a scientific appraisals to motivate the managers.
     该模型为:
短句来源
     Formal Description of TGM Model With RTL Language
     TGM模型RTL形式化描述
短句来源
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This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors. It runs a test program both in the instruction level simulator (ISSim) and in the RTL simulator (RTLSim). From the results of ISSim, we decompose every instruction of the test program into operation sequences on functional units, and obtain the input and output data values of every function unit at any time. By comparing these data values with the simulational results of RTLSim, we can locate the bugs...

This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors. It runs a test program both in the instruction level simulator (ISSim) and in the RTL simulator (RTLSim). From the results of ISSim, we decompose every instruction of the test program into operation sequences on functional units, and obtain the input and output data values of every function unit at any time. By comparing these data values with the simulational results of RTLSim, we can locate the bugs more precisely at the functional unit level. This method can be more effective than traditional methods.

本文提出并实现了一种新的基于指令分解的微处理器验证与RTL级错误定位方法。该方法从指令集模拟器的模拟结果中将指令分解为功能单元上的操作序列,并且输入和输出数据。将该结果与RTL模型的模拟结果比较,使RTL级错误定位精确到功能单元级。相对于传统的方法,大大提高了效率。

A software and hardware co-simulation environment has been built for the HDTV decoder SoC based on MIPS processor core.Using the VMC’s support of MIPS instruction set,and by running the assemble program for test in this environment which connects the VMC model of the MIPS processor core and the RTL model of the HDTV SoC,the software and hardware of SoC synchronously can be debuged,which can lead to a high-efficiency of SoC verification.

针对基于MIPS系列处理器内核的高清电视解码SoC,构建了一个软硬件协同仿真环境。连接MIPS处理器内核的VMC模型和SoC的RTL模型,利用VMC模型支持MIPS指令集的特性运行测试汇编程序,实现了SoC软硬件的同步调试,有效地提高了系统验证的效率。

Dependability plays an important role in the design of nanometer-scale processors and application-specific processors exposed to harsh environments such as cosmic rays. Fault injection is employed to characterize the soft error sensitivity and validate the integrated fault tolerance mechanisms in a fault-tolerant processor. With Godson-1 processor as the research prototype,a novel fault injection technique is presented,which can perform fast and continuous simulation-based fault injections to the subjected processor...

Dependability plays an important role in the design of nanometer-scale processors and application-specific processors exposed to harsh environments such as cosmic rays. Fault injection is employed to characterize the soft error sensitivity and validate the integrated fault tolerance mechanisms in a fault-tolerant processor. With Godson-1 processor as the research prototype,a novel fault injection technique is presented,which can perform fast and continuous simulation-based fault injections to the subjected processor by running two synthesizable processor RTL models simultaneously. Based on this technique,about 30,0000 soft errors are injected into Godson-1 and the soft error sensitivity of Godson-1 is further investigated to direct the design of a fault-tolerant and dependable Godson-1 processor with good statistical significance.

在纳米级制造工艺下以及在航天等特殊应用场合中,可靠性将是处理器设计中的一个重要考虑因素.以龙芯1号处理器为研究对象,探讨了处理器可靠性设计中的故障注入方法,并提出了一种同时运行两个处理器RTL模型的故障注入与分析方法,可以实现连续快速的处理器仿真故障注入.在此基础上,进一步分析了龙芯1号处理器的软错误敏感性,通过快速注入大约30万个软错误,保证了分析结果具有较好的统计意义,可以有效指导后续的容错与可靠性设计.

 
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