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降低功
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  reduce power
     For RISC processor, DVS technique can reduce power by 28.5%.
     对于 RISC微处理器,DVS 技术可以降低功耗 28.5%。
短句来源
     For RISC processer, clock-gating can reduce power by 18.8%.
     对于 RISC 微处理器,门控时钟技术可以降低功耗 18.8%。
短句来源
     The simulation results from the modified CACTI3 show that the proposed TLB structure can reduce power*delay about 85%,80%,66%,and 66%,compared with a FA-TLB,a micro-TLB,a victim-TLB,and a bank-TLB.Therefore the proposed TLB can achieve low power.
     通过改进的CACTI3[2]模拟结果显示:提出的TLB结构比FA-TLB平均功耗×延迟降低约85%,比Micro-TLB降低80%,比Victim-TLB降低66%,比Bank-TLB降低66%以上。 从而,所提出的TLB结构可以达到降低功耗的目的。
短句来源
     Recently with the development of portable electronic products, it is necessary to reduce dropout voltage and quiescent current to extend battery life, reduce power consumption, and improve efficiency of the LDO.
     近年来随着便携式电子产品的发展,特别是采用电池供电的便携式电子产品的迅速发展,为延长电池使用寿命,有效地降低功耗,提高LDO的电源利用率,这就要求LDO具有尽可能低的压差和尽可能小的静态电流。
短句来源
     To reduce power and im prove the speed of circuit,the stati c RAM' s uses Double -Word -Line,Address -Transition -Detecti on and two stage amplifier technologies,so it achieves the fast access time:30ns.
     为了提高电路的速度和降低功耗,采用地址转换监控Address-Translate-Detector(ATD)、两级字线Double-Word-Line(DWL)和新型的两级灵敏放大等技术,其地址取数时间为30ns,最小动态工作电流为30mA(工作电压5V,工作频率2MHz),静态维持电流为1mA。
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  “降低功”译为未确定词的双语例句
     In low-power mode, as the expense of speed, leakage power is reduced by 68%~73% vs. high-speed mode.
     在省电模式下,通过牺牲电路的速度来实现降低功耗的目的,泄漏功耗与高速工作模式相比可以减小约68%~73%。
短句来源
     The development,structure and princple of the polymer light_emitting diode(poly_LED or PLED)and Various approaches to reducing the power dissipation in poly_LED matrix display is described.
     介绍聚合物发光二极管(poly_LED)矩阵显示器的发展历史、结构、原理及降低功耗的方法。
短句来源
     Under 0.35um Si-CMOS process, considering the trade off of accuracy and speed in the ADC, 2.5-bit were converted in the first stage of the pipeline. Using the improved calibration scheme and full difference structure and bottom-plant sampling technique to reduce the errors of the 10-bit (2.5+1.5×5+3), 100Msample/s pipeline ADC.
     在0.35μm工艺水平下,通过折衷考虑提高系统线性度和降低功耗的要求,将流水线第一级精度取为2.5位,采用改进的冗余位算法,并结合全差分结构,下底板采样等技术对一个(2.5+1.5×5+3)结构的10位100Msample/s流水线ADC系统进行校正。
短句来源
     Then the design of low power architectures for programmable signal processors are introduced. the low power feature of the TMS320C55x DSP is investigated finally.
     本文首先叙述可编程信号处理器降低功耗的各种途径,然后介绍低功耗可编程处理器的结构设计,最后对最新的TMS320C55X的低功耗性能进行分析。
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     Based on the analysis of the pipeline structure of a standard 8 bit MCU, a high performance MCU is designed, with low power and high efficiency taken into consideration The efficiency of instruction execution is improved by 2 5 times by optimizing the pipeline structure With the equal operation ability, the power consumption decreases to 1/16 that of the standard structure
     在分析标准 8位 MCU流水线结构的基础上 ,从提高效率及降低功耗的角度出发 ,提出了一个高性能 MCU的实现结构。 通过流水线结构的优化 ,使指令执行效率提高到原来的 2 .5倍 ,在保持运算能力不变的前提下 ,功耗可降为标准结构的 1 /1 6左右
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  相似匹配句对
     L.
     L.
短句来源
     Power Dissipation of Single-Chip System
     降低单片机系统的
短句来源
     Suggestions are given to reduce power dissipation further.
     提出了进一步降低耗的途径。
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     the blood sugar decreased.
     血糖降低
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     The ratio of renal flow volume to cardiac output was also decreased.
     心输出量降低 ;
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  reduce power
This can eliminate the bulky and weighty transformers and reduce power loss.
      
The energy-constraint sensor nodes in WSNs operate on limited batteries, so it is a very important issue to use energy efficiently and reduce power consumption.
      
Finally, female relationships are expected to be constrained by the males' behaviour, especially if they are prone to police female aggressive encounters, which contributes to reduce power differentials among them.
      
Practical application of the MBD technology can be expected to reduce power consumption and therefore operating costs for aerobic fermentation.
      
Results suggest some changes to the pilot plant configuration are necessary to reduce power consumption although maximizing biodigester performance.
      
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Improvement of the button shapes of the rotary bits is one of the most effective approaches to increase the drilling rate and bit-life. A compara-tives test using the equal strength bit buttons and the conventional ones has shown that the former is capable of increasing the volume of rock break-age, reduce the specific power consumption and decrease the critical bit-pressure required. The field test of model KZY-250 Tri-cone bits using equal strength bit buttons in medium hard to hard rocks at Sweichang and...

Improvement of the button shapes of the rotary bits is one of the most effective approaches to increase the drilling rate and bit-life. A compara-tives test using the equal strength bit buttons and the conventional ones has shown that the former is capable of increasing the volume of rock break-age, reduce the specific power consumption and decrease the critical bit-pressure required. The field test of model KZY-250 Tri-cone bits using equal strength bit buttons in medium hard to hard rocks at Sweichang and other three mines has resulted satisfactorily in an increase of drilling rate by 20-30% and a prolongation of bit-life by 70-100% as compared with conventional bit-buttons.

改善钻头的齿形是提高钻进速度和钻头寿命的有效途径之一。用本文所述等强度齿与普通球齿所作的对比试验表明,等强度齿能增大破岩体积,降低功比耗和减小所需的临界钻压。用等强度齿装配的KZY—250三牙轮钻头在裴庄等四个矿的中硬至坚硬矿岩中初步使用,与KY—250球齿钻头比较,钻速提高20—30%,寿命增大70~100%。

The development of microwave communication has brought forward the demand of high quality linear high power amplifier. Feedforward is one of the best techniques to improve the linearity of the power amplifier. However, there exists the drawback of feedforward technique of the power amplifier efficiency reduction. In this paper, the analog predistorter is added before the power amplifier, which is in the feedforward system. The analysis and experiment showed that the efficiency has been notably improved without...

The development of microwave communication has brought forward the demand of high quality linear high power amplifier. Feedforward is one of the best techniques to improve the linearity of the power amplifier. However, there exists the drawback of feedforward technique of the power amplifier efficiency reduction. In this paper, the analog predistorter is added before the power amplifier, which is in the feedforward system. The analysis and experiment showed that the efficiency has been notably improved without the linearity deterioration.

通信技术的发展对于功率放大器的要求越来越高,主要需求集中在高线性高效率的功放。前馈是目前改善功放线性比较好的方法,但是该方法的一个问题是降低了功放的效率。文中使用模拟预失真技术与前馈技术相结合,通过相应的分析与试验,证明该方法可以在不恶化线性指标的前提下提高功放前馈系统的效率。

To design an L-band low harmonics distortion power amplifier,this paper simulates and optimizes linear and nonlinear circuits.It analyzes the characteristics of class AB power amplifier in theory.The harmonics distortion is lowered by using low-pass output matching circuits.After testing,the key performances includes 1dB compression point of 33dBm,frequency band of 1400~1500MHz,gain of 35dB.Good harmonic suppression performance is obtained: at 1480MHz and output power of 33dBm,the second and third harmonics...

To design an L-band low harmonics distortion power amplifier,this paper simulates and optimizes linear and nonlinear circuits.It analyzes the characteristics of class AB power amplifier in theory.The harmonics distortion is lowered by using low-pass output matching circuits.After testing,the key performances includes 1dB compression point of 33dBm,frequency band of 1400~1500MHz,gain of 35dB.Good harmonic suppression performance is obtained: at 1480MHz and output power of 33dBm,the second and third harmonics are as low as70dBc and-63dBc.It shows that the harmonics distortion can be effectively suppressed by optimizing output matching circuits.

针对L频段低谐波失真功率放大器的设计,进行线性与非线性电路分析仿真和电路的优化设计。从理论上分析了甲乙类功率放大器的谐波失真特性,通过采用具有抑制谐波特性的输出匹配电路以降低功放产生的谐波失真。测试得到电路的关键技术指标为:工作频率范围1 390~1 510MHz,增益35 dB,1 dB压缩点33 dBm,并获得了满意的谐波抑制指标,在1 480 MHz、输出功率33dBm时,二、三次谐波分别为-70 dBc和-63 dBc。结果表明在功放设计中,优化设计输出匹配电路可以有效抑制功放的谐波失真。

 
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